soc/intel/cannonlake: Add ramstage uart debug support

Use fixed resources for LPSS uart devices for debugging purpose.

BUG=NONE
BRANCH=NONE
TEST=Boot up with coreboot rom, without this changes, serial log will
stop print anything during PCI resourcre setup as MMIO address of UART
will be re-assigned.

Change-Id: Ib773e01d5f5358f13297400075d6920793200b88
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/intel/cannonlake/Makefile.inc

@@ -37,6 +37,7 @@ ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
 ramstage-y += spi.c
 ramstage-y += systemagent.c
 ramstage-$(CONFIG_UART_DEBUG) += uart.c
+ramstage-$(CONFIG_UART_DEBUG) += uart_pch.c
 ramstage-y += vr_config.c
 
 postcar-y += memmap.c

src/soc/intel/cannonlake/uart_pch.c

@@ -0,0 +1,60 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2017 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <cbmem.h>
+#include <device/pci.h>
+#include <intelblocks/uart.h>
+#include <soc/iomap.h>
+#include <soc/nvs.h>
+#include <soc/pci_devs.h>
+
+void pch_uart_read_resources(struct device *dev)
+{
+	pci_dev_read_resources(dev);
+
+	/* Set the configured UART base address for the debug port */
+	if (IS_ENABLED(CONFIG_UART_DEBUG) && uart_is_debug_controller(dev)) {
+		struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
+		/* Need to set the base and size for the resource allocator. */
+		res->base = UART_BASE_0_ADDR(CONFIG_UART_FOR_CONSOLE);
+		res->size = UART_DEBUG_BASE_0_SIZE;
+		res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
+			IORESOURCE_FIXED;
+	}
+}
+
+bool pch_uart_init_debug_controller_on_resume(void)
+{
+	global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
+
+	if (gnvs)
+		return !!gnvs->uior;
+
+	return false;
+}
+
+device_t pch_uart_get_debug_controller(void)
+{
+	switch (CONFIG_UART_FOR_CONSOLE) {
+	case 0:
+		return PCH_DEV_UART0;
+	case 1:
+		return PCH_DEV_UART1;
+	case 2:
+	default:
+		return PCH_DEV_UART2;
+	}
+}