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mainboard/amd/lamar: Use C89 comments style & remove commented code

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Change-Id: I765814450b82755f84c010f63bc8f919bb0cd4c1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16970
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Elyes HAOUAS 2016-10-10 20:58:29 +02:00 committed by Martin Roth
parent a6b0fc9d7c
commit 767f6e80b7
2 changed files with 26 additions and 29 deletions
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14
src/mainboard/amd/lamar/BiosCallOuts.c
View file

@ -175,8 +175,8 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
/* Thermal Zone Parameter */
FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00;
FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */
FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5;
FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x0e; //6 | BIT3;
FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; /* BIT0 | BIT2 | BIT5 */
FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x0e; /* 6 | BIT3 */
FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00;
FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x54;
FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
@ -212,7 +212,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg0 = 0x00;
FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg1 = 0x01; /* Zone */
FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg2 = 0x55; //BIT0 | BIT2 | BIT5;
FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg2 = 0x55; /* BIT0 | BIT2 | BIT5 */
FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg3 = 0x17;
FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg4 = 0x00;
FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg5 = 0x00;
@ -247,7 +247,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg0 = 0x00;
FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg1 = 0x2; /* Zone */
FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg2 = 0x0; //BIT0 | BIT2 | BIT5;
FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg2 = 0x0; /* BIT0 | BIT2 | BIT5 */
FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg3 = 0x0;
FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg4 = 0x00;
FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg5 = 0x00;
@ -258,7 +258,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg0 = 0x00;
FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg1 = 0x3; /* Zone */
FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg2 = 0x0; //BIT0 | BIT2 | BIT5;
FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg2 = 0x0; /* BIT0 | BIT2 | BIT5 */
FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg3 = 0x0;
FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg4 = 0x00;
FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg5 = 0x00;
@ -268,7 +268,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg9 = 0;
/* IMC Function */
FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x333;//BIT0 | BIT4 |BIT8;
FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x333;/* BIT0 | BIT4 |BIT8 */
/* NOTE:
* FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage,
@ -296,7 +296,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr)
if (StdHeader->Func == AMD_INIT_RESET) {
FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData;
printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
//FchParams->EcChannel0 = TRUE; /* logical devicd 3 */
FchParams->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE);
/* Turn on FCH GPP slots */

3
src/mainboard/amd/lamar/mainboard.c
View file

@ -108,9 +108,6 @@ const u8 mainboard_intr_data[] = {
* use PIC IRQ 10 if it uses PIN A for its hardware INT.
*/
static const struct pirq_struct mainboard_pirq_data[] = {
/* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */
// {GFX_DEVFN, {PIRQ_GFX, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */
// {ACTL_DEVFN, {PIRQ_NC, PIRQ_ACTL, PIRQ_NC, PIRQ_NC}}, /* Audio: 01.1 */
{NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* PCIe J119: 02.1 */
{NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* PCIe J118: 03.1 */
{NB_PCIE_PORT4_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* PCIe J120: 03.2 */