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sandy/ivybridge: Native raminit. 

Based on damo22's work and my X230 tracing.

Works for my X230 in a variety of RAM configs.

Also-By: Damien Zammit <damien@zamaudio.com>
Change-Id: I1aa024c55a8416fc53b25e7123037df0e55a2769
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: http://review.coreboot.org/5786
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This commit is contained in:
Vladimir Serbinenko 2014-05-18 11:05:56 +02:00
parent b37ee1ee7c
commit 7686a56574
21 changed files with 5411 additions and 109 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/cpu/intel/Makefile.inc
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@ -19,6 +19,7 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_RPGA989) += socket_rPGA989
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_NEHALEM) += model_2065x
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += model_206ax
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += model_206ax
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) += model_206ax
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE) += fsp_model_206ax
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_FSP_IVYBRIDGE) += fsp_model_206ax

2
src/cpu/x86/smm/smmhandler_tseg.S
View File

@ -57,7 +57,7 @@
#define SMI_UNLOCKED 1
#define __PRE_RAM__
#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE
#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE
#include <northbridge/intel/sandybridge/sandybridge.h>
#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG)
#elif CONFIG_NORTHBRIDGE_INTEL_NEHALEM

4
src/cpu/x86/smm/smmrelocate.S
View File

@ -48,7 +48,7 @@
#if CONFIG_SMM_TSEG
#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE
#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE
#include <northbridge/intel/sandybridge/sandybridge.h>
#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG)
#elif CONFIG_NORTHBRIDGE_INTEL_NEHALEM
@ -195,7 +195,7 @@ smm_relocate:
xorl %edx, %edx
wrmsr
#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE
#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE
/*
* IED base is top 4M of TSEG
*/

11
src/device/dram/ddr3.c
View File

@ -110,7 +110,7 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd)
{
int ret;
u16 crc, spd_crc;
u8 ftb_divisor, ftb_dividend, capacity_shift, bus_width, sdram_width;
u8 ftb_divisor, ftb_dividend, capacity_shift, bus_width;
u8 reg8;
u32 mtb; /* medium time base */
unsigned int val, param;
@ -209,8 +209,8 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd)
printram(" Invalid SDRAM width\n");
ret = SPD_STATUS_INVALID_FIELD;
}
sdram_width = (4 << val);
printram(" SDRAM width : %u\n", sdram_width);
dimm->width = (4 << val);
printram(" SDRAM width : %u\n", dimm->width);
/* Memory bus width */
reg8 = spd[8];
@ -236,7 +236,7 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd)
* capacity_shift
* The rest is the JEDEC formula */
dimm->size_mb = ((1 << (capacity_shift + (25 - 20))) * bus_width
* dimm->ranks) / sdram_width;
* dimm->ranks) / dimm->width;
/* Fine Timebase (FTB) Dividend/Divisor */
/* Dividend */
@ -334,6 +334,9 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd)
printram(" DIMM Rank1 Address bits mirrored!!!\n");
}
dimm->reference_card = spd[62] & 0x1f;
printram(" DIMM Reference card %c\n", 'A' + dimm->reference_card);
return ret;
}

5
src/include/device/dram/ddr3.h
View File

@ -37,6 +37,7 @@
* @{
*/
#define TCK_1066MHZ 240
#define TCK_933MHZ 275
#define TCK_800MHZ 320
#define TCK_666MHZ 384
#define TCK_533MHZ 480
@ -137,6 +138,8 @@ typedef struct dimm_attr_st {
u16 cas_supported;
/* Flags extracted from SPD */
dimm_flags_t flags;
/* SDRAM width */
u8 width;
/* Number of ranks */
u8 ranks;
/* Number or row address bits */
@ -158,6 +161,8 @@ typedef struct dimm_attr_st {
u32 tWTR;
u32 tRTP;
u32 tFAW;
u8 reference_card;
} dimm_attr;
/** Result of the SPD decoding process */

12
src/mainboard/lenovo/x230/Kconfig
View File

@ -3,7 +3,7 @@ if BOARD_LENOVO_X230
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select CPU_INTEL_SOCKET_RPGA989
select NORTHBRIDGE_INTEL_IVYBRIDGE
select NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE
select SOUTHBRIDGE_INTEL_C216
select EC_LENOVO_PMH7
select EC_LENOVO_H8
@ -18,8 +18,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SERIRQ_CONTINUOUS_MODE
config HAVE_MRC_CACHE
bool
default n
bool
default y
config HAVE_IFD_BIN
bool
@ -41,10 +41,6 @@ config MMCONF_BASE_ADDRESS
hex
default 0xf0000000
config CACHE_ROM_SIZE_OVERRIDE
hex
default 0x800000
config IRQ_SLOT_COUNT
int
default 18
@ -57,7 +53,7 @@ config USBDEBUG_HCD_INDEX
int
default 2
config DRAM_GATE_GPIO
config DRAM_RESET_GATE_GPIO
int
default 10

135
src/mainboard/lenovo/x230/romstage.c
View File

@ -33,7 +33,7 @@
#include <cbmem.h>
#include <console/console.h>
#include "northbridge/intel/sandybridge/sandybridge.h"
#include "northbridge/intel/sandybridge/raminit.h"
#include "northbridge/intel/sandybridge/raminit_native.h"
#include "southbridge/intel/bd82x6x/pch.h"
#include "southbridge/intel/bd82x6x/gpio.h"
#include <arch/cpu.h>
@ -109,66 +109,58 @@ static void rcba_config(void)
RCBA32(BUC) = 0;
}
static void
init_usb (void)
{
const u32 rcba_dump[64] = {
/* 3500 */ 0x20000153, 0x20000153, 0x20000f57, 0x20000f57,
/* 3510 */ 0x20000f57, 0x20000f57, 0x20000153, 0x2000055b,
/* 3520 */ 0x20000153, 0x2000055b, 0x20000f57, 0x20000f57,
/* 3530 */ 0x20000f57, 0x20000f57, 0x00000000, 0x00000000,
/* 3540 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
/* 3550 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
/* 3560 */ 0x024c8001, 0x000024a3, 0x00040002, 0x01000050,
/* 3570 */ 0x02000772, 0x16000f9f, 0x1800ff4f, 0x0001d630,
/* 3580 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
/* 3590 */ 0x00000000, 0x00000000, 0x00000000, 0x00000040,
/* 35a0 */ 0x04000201, 0x00000200, 0x00000000, 0x00000000,
/* 35b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
/* 35c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
/* 35d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
/* 35e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
/* 35f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
};
int i;
/* Activate PMBAR. */
pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE + 4, 0);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */
/* Unlock registers. */
outw (inw (DEFAULT_PMBASE | 0x003c) | 2, DEFAULT_PMBASE | 0x003c);
for (i = 0; i < 64; i++)
write32 (DEFAULT_RCBABASE | (0x3500 + 4 * i), rcba_dump[i]);
pcie_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000);
/* Relock registers. */
outw (0x0000, DEFAULT_PMBASE | 0x003c);
}
void main(unsigned long bist)
{
int boot_mode = 0;
int cbmem_was_initted;
int s3resume = 0;
u32 pm1_cnt;
u16 pm1_sts;
spd_raw_data spd[4];
if (MCHBAR16(SSKPD) == 0xCAFE) {
outb(0x6, 0xcf9);
hlt ();
}
struct pei_data pei_data = {
.pei_version = PEI_VERSION,
.mchbar = DEFAULT_MCHBAR,
.dmibar = DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.smbusbar = SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
.rcba = DEFAULT_RCBABASE,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
.thermalbase = 0xfed08000,
.system_type = 0, // 0 Mobile, 1 Desktop/Server
.tseg_size = CONFIG_SMM_TSEG_SIZE,
.spd_addresses = { 0xA0, 0x00,0xA2,0x00 },
.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
.ec_present = 1,
.gbe_enable = 1,
.ddr3lv_support = 0,
// 0 = leave channel enabled
// 1 = disable dimm 0 on channel
// 2 = disable dimm 1 on channel
// 3 = disable dimm 0+1 on channel
.dimm_channel0_disabled = 2,
.dimm_channel1_disabled = 2,
.max_ddr3_freq = 1600,
.usb_port_config = {
/* enabled usb oc pin length */
{ 1, 0, 0x0080 }, /* P0 (left, fan side), OC 0 */
{ 1, 1, 0x0080 }, /* P1 (left touchpad side), OC 1 */
{ 1, 3, 0x0080 }, /* P2: dock, OC 3 */
{ 1, 0, 0x0040 }, /* P3: wwan, no OC */
{ 1, 0, 0x0080 }, /* P4: Wacom tablet on X230t, otherwise empty */
{ 1, 0, 0x0080 }, /* P5: Expresscard, no OC */
{ 0, 0, 0x0000 }, /* P6: Empty */
{ 1, 0, 0x0080 }, /* P7: dock, no OC */
{ 0, 0, 0x0000 }, /* P8: Empty */
{ 1, 5, 0x0080 }, /* P9: Right (EHCI debug), OC 5 */
{ 1, 0, 0x0040 }, /* P10: fingerprint reader, no OC */
{ 1, 0, 0x0040 }, /* P11: bluetooth, no OC. */
{ 1, 0, 0x0040 }, /* P12: wlan, no OC */
{ 1, 0, 0x0080 }, /* P13: webcam, no OC */
},
.ddr_refresh_rate_config = 2, /* Force double refresh rate */
};
timestamp_init(get_initial_timestamp());
timestamp_add_now(TS_START_ROMSTAGE);
@ -183,6 +175,8 @@ void main(unsigned long bist)
setup_pch_gpios(&x230_gpio_map);
init_usb();
/* Initialize console device(s) */
console_init();
@ -204,7 +198,7 @@ void main(unsigned long bist)
if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
if (acpi_s3_resume_allowed()) {
printk(BIOS_DEBUG, "Resume from S3 detected.\n");
boot_mode = 2;
s3resume = 1;
/* Clear SLP_TYPE. This will break stage2 but
* we care for that when we get there.
*/
@ -218,31 +212,16 @@ void main(unsigned long bist)
/* Enable SPD ROMs and DDR-III DRAM */
enable_smbus();
/* Prepare USB controller early in S3 resume */
if (boot_mode == 2)
enable_usb_bar();
post_code(0x39);
post_code(0x3a);
pei_data.boot_mode = boot_mode;
timestamp_add_now(TS_BEFORE_INITRAM);
/* MRC.bin has a bug and sometimes halts (instead of reboot?).
*/
if (boot_mode != 2)
{
RCBA32(GCS) = RCBA32(GCS) & ~(1 << 5); /* reset */
outw((0 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* let timer go */
}
memset (spd, 0, sizeof (spd));
read_spd (&spd[0], 0x50);
read_spd (&spd[2], 0x51);
sdram_initialize(&pei_data);
if (boot_mode != 2)
{
RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */
outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */
}
init_dram_ddr3 (spd, 1, TCK_800MHZ, s3resume);
timestamp_add_now(TS_AFTER_INITRAM);
post_code(0x3c);
@ -250,13 +229,7 @@ void main(unsigned long bist)
rcba_config();
post_code(0x3d);
quick_ram_check();
post_code(0x3e);
MCHBAR16(SSKPD) = 0xCAFE;
cbmem_was_initted = !cbmem_recovery(boot_mode==2);
if (boot_mode!=2)
save_mrc_data(&pei_data);
#if CONFIG_HAVE_ACPI_RESUME
/* If there is no high memory area, we didn't boot before, so
@ -266,18 +239,14 @@ void main(unsigned long bist)
*(u32 *)CBMEM_BOOT_MODE = 0;
*(u32 *)CBMEM_RESUME_BACKUP = 0;
if ((boot_mode == 2) && cbmem_was_initted) {
if (s3resume) {
void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
if (resume_backup_memory) {
*(u32 *)CBMEM_BOOT_MODE = boot_mode;
*(u32 *)CBMEM_BOOT_MODE = 2;
*(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory;
}
/* Magic for S3 resume */
pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
} else if (boot_mode == 2) {
/* Failed S3 resume, reset to come up cleanly */
outb(0x6, 0xcf9);
hlt();
} else {
pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe);
}

1
src/northbridge/intel/Makefile.inc
View File

@ -15,6 +15,7 @@ subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I5000) += i5000
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_NEHALEM) += nehalem
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += sandybridge
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += sandybridge
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) += sandybridge
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE) += fsp_sandybridge
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_FSP_IVYBRIDGE) += fsp_sandybridge

13
src/northbridge/intel/sandybridge/Kconfig
View File

@ -33,7 +33,15 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE
select DYNAMIC_CBMEM
select CPU_INTEL_MODEL_306AX
if NORTHBRIDGE_INTEL_SANDYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE
config NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE
bool
select CACHE_MRC_BIN
select MMCONF_SUPPORT
select MMCONF_SUPPORT_DEFAULT
select CPU_INTEL_MODEL_306AX
select HAVE_DEBUG_RAM_SETUP
if NORTHBRIDGE_INTEL_SANDYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE
config VGA_BIOS_ID
string
@ -50,7 +58,8 @@ config MRC_CACHE_SIZE
config DCACHE_RAM_BASE
hex
default 0xff7e0000
default 0xff7e0000 if !NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE
default 0xfefe0000 if NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE
config DCACHE_RAM_SIZE
hex

10
src/northbridge/intel/sandybridge/Makefile.inc
View File

@ -25,7 +25,10 @@ ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
ramstage-y += mrccache.c
romstage-y += ram_calc.c
romstage-y += raminit.c
romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += raminit.c
romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += raminit.c
romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) += raminit_native.c
romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) += ../../../device/dram/ddr3.c
romstage-y += mrccache.c
romstage-y += early_init.c
romstage-y += report_platform.c
@ -48,7 +51,10 @@ $(obj)/mrc.cache: $(obj)/config.h
cbfs-files-$(CONFIG_HAVE_MRC_CACHE) += mrc.cache
mrc.cache-file := $(obj)/mrc.cache
mrc.cache-position := 0xfffd0000
mrc-cache-position-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) := 0xfffd0000
mrc-cache-position-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) := 0xfffd0000
mrc-cache-position-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) := 0xfffe0000
mrc.cache-position := $(mrc-cache-position-y)
mrc.cache-type := 0xac
endif

4
src/northbridge/intel/sandybridge/gma.c
View File

@ -650,9 +650,7 @@ static void gma_func0_init(struct device *dev)
physbase = pci_read_config32(dev, 0x5c) & ~0xf;
graphics_base = dev->resource_list[1].base;
int lightup_ok = i915lightup(conf, physbase, iobase, mmiobase, graphics_base);
if (lightup_ok)
gfx_set_init_done(1);
i915lightup(conf, physbase, iobase, mmiobase, graphics_base);
#endif
}

3893
src/northbridge/intel/sandybridge/raminit_native.c Normal file
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File diff suppressed because it is too large Load Diff

29
src/northbridge/intel/sandybridge/raminit_native.h Normal file
View File

@ -0,0 +1,29 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef RAMINIT_H
#define RAMINIT_H
#include <device/dram/ddr3.h>
/* The order is ch0dimmA, ch0dimmB, ch1dimmA, ch1dimmB. */
void init_dram_ddr3(spd_raw_data *spds, int mobile, int min_tck, int s3resume);
void read_spd(spd_raw_data *spd, u8 addr);
#endif /* RAMINIT_H */

639
src/northbridge/intel/sandybridge/raminit_patterns.h Normal file
View File

@ -0,0 +1,639 @@
const u32 pattern[][16] = {
{0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff},
{0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000},
{0xe62d6424, 0x9277e09e, 0x8f43dc3f, 0x76eae589,
0x0010fdc6, 0xdc55e01c, 0x5effb0ab, 0x6cba5d29,
0xa43d1e64, 0xab5c2e0f, 0x7796ed16, 0x96023bf4,
0xa74c831d, 0x90f138c0, 0x17830a8a, 0x5ac17c47},
{0x359ebbeb, 0x2b9b4512, 0xef584d98, 0x106bf7cb,
0x363525ad, 0xb3a4dfdc, 0xa6b9fcd8, 0xd21689ec,
0x84a3695b, 0xbd9c2e27, 0xdb3d0f44, 0x988158f1,
0xcca91d3f, 0xb62a6d12, 0xe905e4cf, 0x7f1fa626},
{0xe58efeae, 0xcd006081, 0xa9119403, 0xbcfbd35f,
0x213b3bf7, 0x7bfcb773, 0xc85143f9, 0x0bdbff50,
0xa3053c90, 0x51d66cb7, 0x296f4387, 0xb715f99e,
0xfaddc989, 0xbb1de8a7, 0x39206b4d, 0x80174a57},
{0xa1622ac1, 0xb4f4a5f0, 0x16dc2bc3, 0x50fb0954,
0x2e261721, 0x52b82c3c, 0x821902b8, 0x0d4b6c38,
0x1f618631, 0x047956f3, 0xd4337f5a, 0x591f8002,
0x27f28db2, 0xfae37369, 0xb3f27580, 0x3cdb6397},
{0x3dee23be, 0x19f36408, 0x227f4a6a, 0x024603c5,
0xd5e062db, 0x6d8d4c5c, 0x7ff693b0, 0x76641be9,
0x9e74f41c, 0xe7bc7f33, 0x2636f2e9, 0x70279750,
0xce2355aa, 0x32d230ef, 0x22f9b468, 0xadd4e7a2},
{0x936c0fed, 0xba0612d5, 0xa97c1ea7, 0x10e29d67,
0x1c4c5dc8, 0x83645621, 0xcd8b521c, 0xb8301817,
0xac7d6571, 0xcc41d200, 0x4ebdefdd, 0xd2917bde,
0x60f75acc, 0x7791534b, 0x26ea2a83, 0x6b74513a},
{0xd1957b85, 0xc6f8f9ca, 0xf04fb4be, 0xfeb786fb,
0xa1dea3aa, 0x67fe7db6, 0x25d49c87, 0xe3d54870,
0x93dc1f86, 0x7d0c1a18, 0x9272e128, 0x68e1b876,
0xce284c9e, 0x8fa18792, 0x5785a340, 0xb6fcf198},
{0xff7d8e4a, 0x0c21ee43, 0xe820b388, 0xb4443c0e,
0xa1e6e498, 0x5c426110, 0x1b434ef3, 0xbef05b91,
0xa6907968, 0x53662ac3, 0x6defac32, 0x2c11c29c,
0x6175cced, 0xb17dd3ad, 0x6e6a1076, 0x1372b1fa},
{0x4408ed06, 0x49460ffd, 0xb49d26cb, 0x6a3662a5,
0x5e857047, 0xa387cd4a, 0x04edc81e, 0xfd94d8d4,
0x2fe48d91, 0x9d2356bc, 0x96131878, 0xaca3fce4,
0xbb312c6c, 0x5023b090, 0x3614be70, 0xa14dfabb},
{0xd4cc1e83, 0x757a1930, 0xc3d16a61, 0x9e0d6681,
0x8a081fa9, 0xbd11c888, 0x1672f010, 0xa083f71c,
0x1ec02eef, 0xc4586ca8, 0x6d322b35, 0x56054679,
0x1552a0ff, 0x5cb7707e, 0xdfb55d4a, 0xcc76cc07},
{0x507cf71f, 0x2166421a, 0x54be4af0, 0xfd42158c,
0x417b1f7f, 0x9466860b, 0x3a0075bf, 0x2055575c,
0xcedfe7ab, 0xbe85aa5f, 0x39d0c2e3, 0x851c19df,
0x39a35a3f, 0x3fb10d7d, 0x20b14899, 0x703b7f08},
{0x8a7d9dd1, 0x33235565, 0xbd3d2e57, 0xa48c2726,
0x0d5e2e13, 0xae421ff9, 0x8784a224, 0xf66c1510,
0x057627aa, 0x8fb0cb41, 0x4289975a, 0xb181adfa,
0x59f2059a, 0xe86feb05, 0x84222fc1, 0x319b3ce9},
{0xe1e243b8, 0x3b0bcc1a, 0x70396f00, 0x5caff44d,
0xe96961b3, 0xad73f692, 0x8b841a2d, 0xf5838839,
0xec9c9d04, 0xcc2b5562, 0xf8ca2549, 0xa9c52ff8,
0x3b2fde68, 0x3d4dc7f0, 0xa57387d0, 0x051199ad},
{0x5f0ce4fc, 0xd830fbb7, 0x90abeb8f, 0x96d9cdbb,
0x58f80a80, 0x0baaca36, 0x81a23623, 0x77127614,
0xaa8382cd, 0x0922fbca, 0xd84d37e1, 0x721297df,
0x160f3b3a, 0x10a1ecdc, 0x151c92f4, 0xc1fdcdab},
{0x261c45cc, 0xfeddd2da, 0xfc3cb1c1, 0x6639641f,
0x2c011892, 0x7108bee2, 0x8545e0b9, 0x7dd36dab,
0x07d91950, 0x1520adcb, 0xf84aa939, 0x07d9bb2d,
0xdf1ed826, 0xaee3c814, 0x1dca1e81, 0xc8e9f486},
{0x933d306a, 0xaab7103d, 0xa8be37be, 0x49612f3a,
0xb0cf28e5, 0xf9648902, 0x106d7c11, 0xf32e1813,
0x21af36ef, 0xe695e4c4, 0x7ee1831d, 0x2aeda467,
0x99d0c655, 0x3f0691ab, 0xcd68f7c1, 0xb469a20e},
{0x8557aef0, 0x3eb0e373, 0x0853ac31, 0xe5bded62,
0x3eddb0dd, 0x6bbf1caf, 0x2119c3d9, 0xe1732350,
0x55456c75, 0xf6119375, 0x498dd1ad, 0x13f80916,
0xb97f9f5e, 0x921d9f4c, 0xabdee367, 0x1d6bb8bf},
{0xd165a3be, 0xd8b41598, 0xa20e1809, 0xefd5c8ce,
0x18935c80, 0xdf1911f9, 0xc9e449eb, 0xb887a4d7,
0x4a324f6f, 0x533e8031, 0x1c21c074, 0xa95f1ea5,
0x765b320a, 0x839d7dfb, 0xc7d3aa93, 0xe534ae3d},
{0xbe8592c8, 0x068457e6, 0x89b94fa3, 0xd522ad02,
0x7e7db0b7, 0x2c5b896f, 0x9f8ecb37, 0x05b983ff,
0x3fe9b25f, 0x34a6215b, 0x0592ba34, 0xd564f85a,
0x156c426d, 0x25ad5460, 0xe7b5e8b7, 0xa73285c6},
{0x5ad8d838, 0x27b42d36, 0xcc806ad1, 0x157a058a,
0x7297735a, 0xffd6df8d, 0xff96f7a2, 0x155b27ea,
0x84708101, 0x979fd78b, 0x49797d0c, 0x0dc93e3c,
0x20287332, 0xed759f88, 0xe5068529, 0xb83aa781},
{0xc38b302c, 0x57b54075, 0xac810692, 0xb0d493e7,
0x4adda486, 0x0665ce2e, 0xb2a9c003, 0xafacc4ce,
0x4d5e906d, 0xb3d52fab, 0xe6962c6b, 0x850f4dd1,
0x5021656c, 0x5df6c06b, 0x9255125b, 0x2363c478},
{0x188b715c, 0xe8b884b0, 0x5e6d0b9a, 0x1f0051e1,
0xd2d35d4c, 0xbfeaecbe, 0xc84bb0ad, 0x67a232d6,
0x99001587, 0xbf4313e1, 0x74f64061, 0x2c1fc562,
0xb6fe8ca6, 0x5226a239, 0xf5198574, 0x61b51dca},
{0x51dcecd3, 0xbadbe596, 0xebe3e84a, 0x772bfdfc,
0x03656ac5, 0xa7c36e91, 0x6cd32cf0, 0xc3f699dd,
0x7d5aba01, 0x51e38e82, 0x23103a98, 0x20298b9d,
0x19436510, 0x63ad7e6c, 0x8bc2b33f, 0x27079917},
{0x8bd5be78, 0xf2403bfa, 0x780ebdb6, 0x94c53b64,
0x6241c2e2, 0x5bfb081e, 0x6799e88f, 0xc997b7d1,
0x466ac8b1, 0xbf5909da, 0x497ea39f, 0x402ffb48,
0xd7470c2d, 0x8510aba9, 0x6c52a1c9, 0x812ca967},
{0x031f7ab4, 0xd32fe890, 0x36ae6de5, 0x083dcde4,
0x99a7f12f, 0xe44864a7, 0x02b75fff, 0xf25dda35,
0x7679ff4f, 0xed421e01, 0xd9c2cfa1, 0xd36b4e82,
0x5315d908, 0xc7ebcb2a, 0xb6f3e4c1, 0xf5bfbae9},
{0x3f4a2a96, 0x64d8bd5a, 0x19acd70d, 0xf62fcdd9,
0x5de99cdf, 0x32f3b7cb, 0x2c020578, 0x4e9bafb8,
0x74919a08, 0xaba33e91, 0xa6bd2254, 0x2435a9b9,
0x47e2a1b4, 0xe837a28e, 0xe113f1b0, 0x7654bd79},
{0x05537a6c, 0x77be1a5c, 0x4c7492c9, 0x9086bfb0,
0x257adc18, 0xf4787fc1, 0xe3fb6d53, 0x9525e589,
0x445a65bc, 0x833f7d08, 0x69cf1f7e, 0x9a6372e1,
0xceedb52e, 0x31032997, 0xd1c36828, 0x132772d6},
{0x0a166972, 0x89beaf3b, 0x8d780fbc, 0x8aea5392,
0x58347a41, 0x1e381ec2, 0xcc6280c8, 0xee0863e1,
0x976e2dd2, 0x8c6ee6e2, 0xa0ca57cd, 0x95114a7d,
0x3c096704, 0xa941769d, 0x2de20c05, 0x0bf8f812},
{0x22779d6c, 0x94e12e8f, 0x5ce40299, 0xea1b55b0,
0x9ebec05d, 0xe076cd2b, 0x8fef5648, 0x6a284c65,
0xa790b705, 0xf0b19997, 0x0d8ca8af, 0x17440419,
0xef4f702f, 0x33cbcbb1, 0x83d60f26, 0x48988397},
{0x0fed7f53, 0xb5acbb67, 0xc031c73f, 0x5364d9ef,
0xa6dbd12d, 0x82174a6c, 0xccf8e7ab, 0xc473c036,
0xcff493d8, 0xad9afc3b, 0x316a24e8, 0x1842bea4,
0x4cc0c82e, 0x28ccd91e, 0xd7311b5d, 0x50a89860},
};
static const u8 use_base[63][32] = {
{
0x0e, 0x9e, 0xa1, 0x39, 0x06, 0x26, 0xc5, 0xe9, 0xed, 0x07, 0x49, 0x3b, 0x34, 0x7f, 0x1c, 0xa8,
0xdf, 0x7b, 0xb7, 0xb8, 0x28, 0xbe, 0x8a, 0x70, 0x17, 0xe5, 0xc0, 0x44, 0x4a, 0x8e, 0x61, 0x3b,
},
{
0x42, 0xe6, 0xe0, 0x6a, 0xb3, 0x08, 0x28, 0xaf, 0xfa, 0xb9, 0xb7, 0x32, 0x83, 0x5c, 0xef, 0x3d,
0x90, 0x91, 0x64, 0x31, 0xe9, 0x3c, 0x92, 0xe6, 0xa3, 0xd4, 0x6a, 0xc6, 0x01, 0xa6, 0xeb, 0xe6,
},
{
0x39, 0x7f, 0x6f, 0x81, 0xb4, 0x33, 0x4a, 0xde, 0x4f, 0x77, 0x28, 0x47, 0x08, 0xf9, 0x3a, 0x55,
0x21, 0x57, 0x27, 0x59, 0xf5, 0x96, 0xad, 0xc1, 0x10, 0x33, 0xe0, 0xe2, 0xf8, 0xb6, 0x49, 0xbd,
},
{
0xdf, 0x57, 0x60, 0x27, 0x95, 0x50, 0x3a, 0x8c, 0x34, 0x8b, 0xae, 0xc5, 0x69, 0x26, 0xca, 0x39,
0x55, 0x98, 0xfb, 0x05, 0x3c, 0x1c, 0x8d, 0xf8, 0xb9, 0x99, 0x05, 0x40, 0xe5, 0x5e, 0x2f, 0xf6,
},
{
0xc1, 0x6a, 0xea, 0xd6, 0x39, 0x56, 0x08, 0x89, 0x83, 0x4c, 0xef, 0xda, 0xb2, 0x69, 0x76, 0xe4,
0x75, 0x3f, 0x39, 0x13, 0x96, 0xb5, 0x41, 0x84, 0x00, 0x64, 0x79, 0x47, 0xe4, 0xcb, 0xc3, 0xd0,
},
{
0xf8, 0xb1, 0x19, 0x76, 0x51, 0x99, 0xd7, 0x45, 0x38, 0x40, 0xbf, 0x10, 0x4c, 0x89, 0x43, 0xa9,
0x89, 0xe2, 0x85, 0x3f, 0xb4, 0xe8, 0xbf, 0x5e, 0xc2, 0xb4, 0x16, 0x6d, 0x1c, 0x61, 0xca, 0x40,
},
{
0x1c, 0xdc, 0xa6, 0xdb, 0x71, 0x8b, 0xf9, 0xbb, 0xee, 0xc2, 0xa5, 0x66, 0xa4, 0xbc, 0xb6, 0x89,
0x58, 0xb9, 0x6f, 0x57, 0x71, 0x57, 0x5c, 0xf0, 0xed, 0xcf, 0x2c, 0x2e, 0x1d, 0x34, 0xc3, 0x00,
},
{
0x1d, 0x30, 0x03, 0xb9, 0x15, 0x8e, 0x47, 0x8c, 0xf2, 0x4e, 0x2d, 0xf1, 0xbf, 0x96, 0xa7, 0xa1,
0x3f, 0x26, 0xc3, 0xc9, 0x08, 0x0b, 0xa8, 0xdd, 0x9b, 0xeb, 0xbc, 0x77, 0x1c, 0x10, 0x03, 0x77,
},
{
0x50, 0x7e, 0x62, 0x26, 0xcb, 0x49, 0x7b, 0x1a, 0xd4, 0x54, 0xf1, 0x25, 0x3d, 0xa2, 0xe6, 0x8a,
0xb3, 0x62, 0xf1, 0x7e, 0x03, 0xef, 0x1b, 0x27, 0x21, 0xcc, 0xfc, 0x72, 0x30, 0x0c, 0x69, 0xad,
},
{
0x11, 0xf5, 0xb2, 0xfa, 0x2d, 0xbc, 0xa1, 0xd9, 0x74, 0x15, 0x59, 0xf2, 0xc6, 0x66, 0x4f, 0xde,
0x84, 0x82, 0x4f, 0xe8, 0x33, 0xd5, 0xc5, 0xdd, 0xba, 0x0c, 0xc7, 0x51, 0x1f, 0x3c, 0x6d, 0x44,
},
{
0xcf, 0xf5, 0x3b, 0xc1, 0xbd, 0x5f, 0x9c, 0xad, 0x57, 0xfb, 0xfc, 0xbe, 0x95, 0xa0, 0x48, 0x58,
0x8a, 0x68, 0x97, 0x71, 0xf3, 0xc0, 0xd1, 0x31, 0x33, 0xb9, 0x3c, 0xe9, 0x4f, 0xbb, 0x8d, 0xeb,
},
{
0x29, 0x0c, 0xa1, 0xc8, 0x04, 0xdc, 0xf9, 0x25, 0x85, 0x7e, 0xea, 0x6d, 0x75, 0x28, 0x69, 0x3f,
0x3a, 0x83, 0xe4, 0x33, 0x31, 0x77, 0x57, 0x2e, 0xa9, 0xa8, 0x05, 0xfe, 0x19, 0xb7, 0xc4, 0xd1,
},
{
0x6d, 0x5d, 0x3f, 0x4f, 0x8a, 0x6a, 0x77, 0x2d, 0xf7, 0x9f, 0x73, 0xab, 0x40, 0xd9, 0x89, 0x57,
0x69, 0xd7, 0xc8, 0xc3, 0x69, 0x54, 0x93, 0x7c, 0x9f, 0x4a, 0xcc, 0xaf, 0xcc, 0x0e, 0xe0, 0xb8,
},
{
0xb6, 0xd5, 0x36, 0x3f, 0x1c, 0x34, 0x54, 0x9b, 0xfc, 0xec, 0x5b, 0xb0, 0x26, 0xa6, 0xc0, 0x61,
0x6d, 0x4c, 0x4f, 0x86, 0x2a, 0xbd, 0x34, 0x35, 0x52, 0x2c, 0x82, 0x01, 0x66, 0x0e, 0x80, 0x01,
},
{
0x48, 0x39, 0x43, 0xb8, 0xf9, 0x2b, 0x25, 0xe8, 0xf7, 0xf0, 0x1a, 0xed, 0x33, 0x1e, 0x30, 0xba,
0x15, 0x37, 0xeb, 0xae, 0x97, 0xa7, 0x36, 0xa4, 0xc7, 0x1f, 0x91, 0x01, 0x38, 0x80, 0x5a, 0x76,
},
{
0x74, 0xbe, 0x15, 0x6b, 0x85, 0x28, 0xe4, 0xc4, 0x13, 0x68, 0x67, 0x03, 0x27, 0x7e, 0x32, 0x08,
0x87, 0x23, 0xda, 0xf2, 0x47, 0xdd, 0xac, 0x2c, 0xc5, 0x7f, 0x06, 0xc8, 0x17, 0x4c, 0x6c, 0x81,
},
{
0x0d, 0x9f, 0x68, 0xbb, 0xa6, 0x6c, 0x7d, 0x3f, 0x81, 0xcf, 0x9a, 0x52, 0x87, 0xce, 0x98, 0x25,
0x40, 0x2b, 0x1b, 0xdf, 0xd3, 0x6b, 0x53, 0xed, 0x80, 0xd2, 0x3d, 0xca, 0xdf, 0x07, 0x4e, 0x6b,
},
{
0xff, 0xf1, 0xd2, 0x1f, 0xbd, 0xd6, 0xa7, 0x3d, 0xb4, 0xc6, 0x88, 0x9d, 0x7b, 0x05, 0x04, 0x0b,
0x4c, 0x6f, 0x11, 0x7f, 0x19, 0x18, 0x48, 0xf1, 0x26, 0xad, 0xd0, 0x60, 0xfa, 0x40, 0x35, 0xbb,
},
{
0xae, 0xec, 0x0e, 0x2e, 0xfd, 0x46, 0xf0, 0x9c, 0x06, 0x1b, 0x62, 0xbf, 0xf0, 0x3e, 0xba, 0xdf,
0xb2, 0xa2, 0x83, 0x83, 0xda, 0x04, 0x15, 0xec, 0x1e, 0x2e, 0x1a, 0x64, 0x08, 0x8e, 0xd3, 0x87,
},
{
0x61, 0x14, 0x05, 0x0b, 0xdb, 0xf4, 0xf0, 0xa3, 0x41, 0x11, 0x7b, 0xd9, 0xa1, 0x40, 0x4f, 0x62,
0x98, 0x37, 0xa0, 0x90, 0x3d, 0x78, 0x63, 0x24, 0xbc, 0x8e, 0x9e, 0x99, 0x2e, 0xc7, 0xb1, 0x6d,
},
{
0x0f, 0xf1, 0x5f, 0xe4, 0x94, 0x3d, 0x24, 0x0d, 0xa2, 0xcf, 0xed, 0xbb, 0x55, 0x8e, 0xdb, 0x07,
0x12, 0x05, 0x79, 0x82, 0xb1, 0x3a, 0x71, 0x76, 0xbb, 0x8b, 0xcb, 0xcc, 0x00, 0x40, 0x2e, 0xab,
},
{
0x48, 0x59, 0xfa, 0x46, 0x15, 0x5e, 0xa2, 0x0d, 0xe8, 0x81, 0x69, 0xe6, 0x2f, 0x5f, 0x6d, 0xaf,
0xad, 0xc7, 0x30, 0xd6, 0xec, 0x03, 0x1e, 0x19, 0xdd, 0x1d, 0x00, 0x94, 0x0b, 0x93, 0x5a, 0x28,
},
{
0xfa, 0x64, 0x62, 0x57, 0x02, 0x7e, 0x37, 0xb8, 0x10, 0xa9, 0x4b, 0xe7, 0xbf, 0x03, 0xdc, 0x1c,
0xe7, 0x21, 0x68, 0x60, 0x53, 0xec, 0xf0, 0xfc, 0xbf, 0xe5, 0x8e, 0xca, 0x77, 0xdb, 0xa5, 0xae,
},
{
0xc1, 0xa9, 0x9f, 0xc2, 0x87, 0x11, 0xad, 0x1c, 0xc5, 0x56, 0x61, 0xc0, 0x20, 0x33, 0xc9, 0x85,
0xf0, 0x81, 0x36, 0x18, 0xdb, 0xaa, 0x7e, 0x79, 0x36, 0x2d, 0xfc, 0x8f, 0x72, 0x3c, 0x4c, 0xa3,
},
{
0xb4, 0xd3, 0x38, 0xed, 0xd3, 0x6c, 0x03, 0x26, 0x0e, 0x1c, 0x8a, 0xa8, 0x72, 0x17, 0xcb, 0xf7,
0x87, 0xf3, 0x3f, 0x73, 0x5d, 0x12, 0xe8, 0x3b, 0x55, 0xb6, 0xcc, 0xc6, 0x85, 0xad, 0x9f, 0x9e,
},
{
0xe9, 0x97, 0xde, 0x7f, 0xe0, 0x9a, 0xc1, 0xdc, 0x96, 0x4c, 0xc3, 0x0d, 0x2d, 0xd4, 0x98, 0x54,
0x89, 0x1c, 0x57, 0x7d, 0x17, 0x96, 0xe9, 0x2f, 0x02, 0x73, 0x07, 0x5c, 0x8b, 0x44, 0xd7, 0x75,
},
{
0xaf, 0xf2, 0x39, 0xc4, 0x23, 0xff, 0xd5, 0x85, 0xf3, 0x11, 0x44, 0x9e, 0xab, 0x59, 0x29, 0x33,
0xe6, 0xc2, 0x1d, 0xba, 0xa8, 0x5b, 0x70, 0xc3, 0xc0, 0xf8, 0x56, 0x3b, 0x8e, 0x43, 0x4c, 0x4b,
},
{
0x46, 0x93, 0xb5, 0x8a, 0x71, 0x67, 0xcb, 0x42, 0x6b, 0x1b, 0x43, 0x58, 0x8b, 0x18, 0xb9, 0xf3,
0xdc, 0x91, 0x1c, 0x08, 0x83, 0xe3, 0x63, 0xfa, 0xf9, 0x99, 0x99, 0xcb, 0x05, 0x15, 0x7b, 0x85,
},
{
0xcf, 0xc6, 0x3c, 0x01, 0xbd, 0xfb, 0x00, 0x8c, 0x8b, 0x07, 0x69, 0xac, 0x61, 0xdb, 0x30, 0xd5,
0x7c, 0x71, 0x98, 0x69, 0x2e, 0x4a, 0x4a, 0x44, 0xe4, 0x72, 0x6f, 0xf2, 0x9d, 0x58, 0x02, 0x23,
},
{
0x29, 0x10, 0xe1, 0xe5, 0x3f, 0xe6, 0x26, 0xaf, 0x30, 0x3c, 0xfe, 0x1f, 0x97, 0x21, 0xdd, 0x8c,
0xbb, 0x90, 0xdb, 0x2a, 0xb5, 0xb4, 0x46, 0x43, 0x50, 0x0b, 0x6b, 0xa8, 0x8f, 0x55, 0xfb, 0xd2,
},
{
0x89, 0x56, 0x19, 0xf9, 0x4a, 0xec, 0x38, 0x99, 0xaa, 0xcc, 0xc5, 0x15, 0xdf, 0x19, 0xee, 0x1a,
0xc0, 0x94, 0xaf, 0x0f, 0x7b, 0xf4, 0x06, 0xf1, 0x70, 0xa3, 0x79, 0x06, 0xba, 0x4e, 0x09, 0xa6,
},
{
0x53, 0x3a, 0x35, 0x98, 0xa9, 0xcb, 0x2c, 0x72, 0x73, 0xb2, 0xb0, 0x63, 0x38, 0xfc, 0xa3, 0xa5,
0xa3, 0xf1, 0x4d, 0x04, 0x2f, 0x1b, 0x83, 0xbd, 0xed, 0x20, 0x8e, 0xa5, 0x1e, 0x9d, 0xd6, 0x69,
},
{
0x78, 0x44, 0xe3, 0x22, 0xa4, 0x7c, 0x53, 0xef, 0x60, 0x8e, 0x39, 0x95, 0x7d, 0x9d, 0x3d, 0x0b,
0x4a, 0x4f, 0xf4, 0x73, 0xf8, 0xfe, 0xe7, 0x65, 0x86, 0x72, 0x13, 0x0b, 0x4e, 0x8f, 0x4d, 0x7b,
},
{
0x46, 0xba, 0xd2, 0x82, 0x46, 0x18, 0x6e, 0x46, 0x96, 0x05, 0x1d, 0xfb, 0xf6, 0xde, 0xba, 0xb5,
0x6b, 0x73, 0x7a, 0xd5, 0x76, 0x11, 0xb7, 0x7c, 0x0d, 0x61, 0xba, 0xf9, 0x05, 0x12, 0x2b, 0x4e,
},
{
0x41, 0x08, 0x8b, 0x63, 0x10, 0xeb, 0x85, 0x10, 0xf3, 0x05, 0x84, 0xc0, 0x81, 0x1f, 0x7f, 0xd3,
0x9d, 0x01, 0xdc, 0x32, 0xd0, 0xe2, 0xd1, 0xd1, 0x41, 0x8a, 0xa0, 0xf2, 0x64, 0xda, 0x8b, 0x0e,
},
{
0x99, 0xf1, 0xf2, 0x88, 0xe8, 0x72, 0x8b, 0x40, 0x17, 0xcc, 0xa7, 0x4c, 0x7d, 0xf1, 0xc4, 0x3f,
0xbf, 0xf8, 0xbe, 0xc9, 0xce, 0xce, 0x2b, 0xe9, 0x4d, 0x5b, 0xd1, 0xef, 0x76, 0xae, 0x3b, 0xbb,
},
{
0x64, 0x69, 0x47, 0x03, 0xe9, 0x3b, 0xc2, 0x2d, 0x2d, 0x1a, 0xdd, 0xa4, 0xac, 0xb6, 0x6e, 0x7a,
0x41, 0x7d, 0x82, 0xed, 0x54, 0xf7, 0x05, 0xd8, 0xae, 0x07, 0x6c, 0x1c, 0xf6, 0x51, 0xa1, 0xc0,
},
{
0x84, 0xaf, 0xe8, 0x59, 0x0c, 0x14, 0x24, 0xec, 0xa0, 0xd2, 0xf3, 0x8f, 0x2f, 0x22, 0xe4, 0x52,
0xf8, 0xa7, 0x39, 0x74, 0x7f, 0x80, 0x23, 0x3f, 0x30, 0xe3, 0xcb, 0x26, 0x12, 0x5c, 0xa7, 0x93,
},
{
0x48, 0xc8, 0x41, 0x42, 0xc5, 0xe7, 0x4d, 0x91, 0x54, 0xa6, 0x5b, 0xba, 0x46, 0x89, 0xd5, 0x42,
0x46, 0xbc, 0xf2, 0x67, 0x4a, 0xf9, 0x88, 0xe9, 0x02, 0xa5, 0xc2, 0x38, 0x9d, 0x6a, 0x75, 0xcd,
},
{
0xab, 0x9b, 0x2c, 0x09, 0xda, 0xaa, 0xe9, 0xe2, 0xd7, 0xf1, 0xa4, 0x86, 0x41, 0x14, 0xcb, 0x4e,
0x2b, 0xd1, 0x5a, 0x9a, 0x46, 0x47, 0x90, 0xb2, 0x63, 0x16, 0xcb, 0x60, 0x1c, 0x12, 0xe3, 0x2b,
},
{
0x54, 0x21, 0xc0, 0xbc, 0xb8, 0x29, 0xce, 0xa4, 0xf2, 0x38, 0xb4, 0x0d, 0x7d, 0xfa, 0xd4, 0x3e,
0x28, 0xf4, 0xc4, 0xf4, 0x4a, 0x9f, 0x11, 0xf2, 0xe2, 0x31, 0xa3, 0x72, 0x16, 0xbb, 0xd9, 0x05,
},
{
0xdc, 0x6e, 0xbe, 0x64, 0xa2, 0xb2, 0x64, 0x46, 0x00, 0xee, 0xd2, 0xa5, 0x81, 0x86, 0x44, 0xa4,
0x5c, 0xc4, 0xba, 0xc4, 0xa2, 0x44, 0x36, 0x77, 0xb2, 0xec, 0x0d, 0xbe, 0x8f, 0xc0, 0x80, 0x6f,
},
{
0x51, 0x51, 0xb2, 0x50, 0x11, 0x0b, 0x60, 0xb8, 0x8e, 0xc2, 0xf7, 0xa8, 0xb4, 0xd2, 0x48, 0xc3,
0x51, 0x43, 0x52, 0xeb, 0x37, 0xac, 0xd0, 0xf7, 0x61, 0xa1, 0xe9, 0xe3, 0xa7, 0xdf, 0x26, 0xa9,
},
{
0x10, 0xd9, 0xf2, 0xfe, 0x71, 0x8e, 0x49, 0x2c, 0x64, 0x53, 0xb0, 0x9e, 0x7a, 0xcc, 0x86, 0xab,
0x06, 0xd7, 0xc7, 0x13, 0xd1, 0xcb, 0x21, 0x42, 0x97, 0x29, 0x5d, 0xff, 0xaa, 0xec, 0x52, 0x40,
},
{
0x7b, 0x35, 0x93, 0xb9, 0xca, 0xbb, 0x7e, 0x09, 0x8f, 0x34, 0x32, 0x02, 0xe7, 0x0c, 0xcf, 0xd1,
0x6c, 0x2d, 0x11, 0xcd, 0xa5, 0x3b, 0xba, 0x14, 0x47, 0xc5, 0x2c, 0xb8, 0xf6, 0xfb, 0x9d, 0x77,
},
{
0x45, 0xce, 0x12, 0x8e, 0xa2, 0x4e, 0x56, 0x58, 0xa7, 0xcf, 0x26, 0x4e, 0x32, 0x21, 0xe0, 0x2b,
0xed, 0x8d, 0xe2, 0xd9, 0x51, 0x32, 0x9b, 0xdc, 0x7b, 0x0e, 0x14, 0x0a, 0xdb, 0x63, 0x6b, 0x42,
},
{
0x9d, 0x49, 0x72, 0xea, 0x89, 0xc7, 0xa2, 0xfd, 0x9a, 0x55, 0xd7, 0x05, 0x16, 0xeb, 0xf7, 0x49,
0xb6, 0xcf, 0x56, 0xf7, 0x2b, 0xef, 0x6d, 0xbe, 0xdd, 0x0e, 0x90, 0x01, 0xaf, 0x1b, 0xbb, 0xaa,
},
{
0x2c, 0xb7, 0x26, 0x43, 0x02, 0xc5, 0x7b, 0xc6, 0x71, 0x1f, 0xf2, 0x28, 0xb4, 0xea, 0x5f, 0x02,
0xc6, 0xeb, 0xb4, 0xf7, 0x6f, 0x01, 0x7f, 0xfe, 0x3a, 0xb0, 0xe3, 0xf3, 0x31, 0xd3, 0xcb, 0x0f,
},
{
0x75, 0x54, 0x90, 0xec, 0xed, 0xcc, 0xbc, 0x5c, 0x9b, 0x44, 0x30, 0x57, 0x57, 0xe0, 0xec, 0x58,
0x20, 0x54, 0x20, 0xb0, 0x92, 0x3a, 0x06, 0x9f, 0x69, 0xcb, 0x88, 0xee, 0x52, 0x6e, 0x4c, 0xf6,
},
{
0x2a, 0x08, 0xd8, 0xdd, 0x2e, 0x07, 0x54, 0x0b, 0x37, 0xc6, 0x09, 0x26, 0x98, 0xf7, 0x45, 0xf6,
0x05, 0x4f, 0x35, 0xe6, 0xb0, 0x44, 0xff, 0x62, 0x89, 0x47, 0x69, 0x30, 0xea, 0x3b, 0x7b, 0x81,
},
{
0x0f, 0x7f, 0x34, 0xbf, 0xf9, 0xce, 0xe7, 0x4c, 0xe1, 0x7a, 0x24, 0x74, 0xeb, 0x8b, 0xb0, 0x65,
0x18, 0x19, 0xaf, 0x44, 0x45, 0x5e, 0xd9, 0xa4, 0xf0, 0xd8, 0xe8, 0x09, 0x22, 0x58, 0x4e, 0x4d,
},
{
0x48, 0x41, 0x7a, 0xd2, 0x26, 0xda, 0x39, 0xb2, 0xba, 0x03, 0x17, 0xe9, 0x80, 0x8e, 0x53, 0x4c,
0xac, 0x64, 0x6b, 0xa7, 0x5f, 0xed, 0x64, 0x60, 0xb7, 0x5e, 0x7a, 0x68, 0x1a, 0x8a, 0xda, 0x2b,
},
{
0x52, 0x01, 0x25, 0xb0, 0x59, 0xcf, 0x61, 0x30, 0x52, 0xe7, 0x77, 0x66, 0xc9, 0x35, 0xac, 0xfe,
0xc0, 0xa2, 0x18, 0x58, 0xf1, 0xc1, 0x8f, 0x28, 0x72, 0x2f, 0xdc, 0x36, 0x10, 0x5b, 0xd9, 0x6f,
},
{
0x05, 0xbf, 0x47, 0x32, 0x0e, 0xa7, 0xc6, 0xd6, 0x13, 0xa1, 0x72, 0x38, 0x8c, 0x1a, 0xbc, 0x6d,
0x7c, 0xd8, 0x34, 0xac, 0x69, 0x5b, 0x43, 0xc4, 0x00, 0xf8, 0xf2, 0xa7, 0xaf, 0x9f, 0xb0, 0xde,
},
{
0x54, 0x67, 0xce, 0xf2, 0xfc, 0x91, 0xd2, 0x4d, 0x73, 0xc6, 0xc9, 0xc3, 0xfe, 0xcf, 0x72, 0xa0,
0xc7, 0x43, 0xff, 0x87, 0x4b, 0xe3, 0x7f, 0xba, 0xd4, 0xa2, 0xa3, 0x14, 0x8f, 0xa0, 0x39, 0x91,
},
{
0xbd, 0x24, 0x35, 0xb5, 0x0e, 0x7a, 0x13, 0xb3, 0x92, 0x83, 0xaa, 0xbd, 0x0c, 0x22, 0x93, 0xbb,
0x2a, 0xe7, 0x7a, 0x56, 0x2d, 0xae, 0x41, 0x62, 0x52, 0xb2, 0xe9, 0xbd, 0x29, 0x05, 0x51, 0x95,
},
{
0x97, 0x8f, 0x21, 0x82, 0x72, 0x4f, 0x65, 0xc8, 0xfc, 0x2e, 0x5e, 0x8a, 0x1a, 0xce, 0x34, 0x39,
0x12, 0xe6, 0x9b, 0xc3, 0xab, 0x51, 0xa9, 0x40, 0xf7, 0xbe, 0x94, 0xd0, 0x66, 0xda, 0xa5, 0x39,
},
{
0x5a, 0x48, 0x43, 0x9a, 0x8e, 0x22, 0x85, 0x9b, 0x28, 0xc9, 0x63, 0xa2, 0x57, 0xa6, 0xe2, 0x16,
0x64, 0xec, 0x3c, 0x59, 0x13, 0xc4, 0x7b, 0x51, 0xea, 0xfe, 0x2e, 0x70, 0xbd, 0xd9, 0x77, 0x85,
},
{
0x2b, 0x74, 0xb6, 0x95, 0x18, 0x94, 0x54, 0x6d, 0xae, 0xdd, 0xe9, 0xb2, 0xf9, 0xbd, 0xce, 0x27,
0xa9, 0x87, 0x42, 0x13, 0x22, 0x29, 0x87, 0x7a, 0x04, 0xe3, 0xbe, 0x2f, 0x9c, 0x18, 0xbb, 0x13,
},
{
0x80, 0x95, 0x43, 0xaa, 0x19, 0x90, 0x03, 0x4f, 0x47, 0xbf, 0xf5, 0x8e, 0x2d, 0x55, 0x23, 0xb7,
0x7b, 0x5d, 0xaa, 0x34, 0x37, 0xb2, 0x70, 0x86, 0x5e, 0xc4, 0x94, 0xf3, 0x61, 0xfd, 0x87, 0x65,
},
{
0xd4, 0xbc, 0x03, 0x65, 0xb0, 0xc5, 0x44, 0x81, 0x7b, 0x06, 0x94, 0x79, 0xca, 0x1f, 0xe2, 0x28,
0x53, 0xc8, 0xa7, 0x10, 0x13, 0x77, 0xb7, 0x5c, 0x9a, 0x34, 0x1e, 0xd5, 0x78, 0xb1, 0x21, 0x61,
},
{
0x90, 0x0e, 0x7f, 0xa3, 0x24, 0x18, 0x12, 0xbf, 0x45, 0xd2, 0x52, 0xa3, 0x99, 0x74, 0x89, 0xd2,
0x12, 0x8d, 0x32, 0x3c, 0xd0, 0x28, 0x54, 0x98, 0x6c, 0x9e, 0xdd, 0xc0, 0xd5, 0xf1, 0x8a, 0xb1,
},
{
0x82, 0xad, 0x7a, 0x5c, 0x4d, 0x81, 0x54, 0x41, 0x79, 0x42, 0x54, 0x5c, 0x49, 0x41, 0xed, 0x49,
0xc7, 0x06, 0x61, 0xbb, 0x89, 0x2b, 0x90, 0x04, 0x1f, 0x8c, 0x31, 0x3b, 0x39, 0x4f, 0xf8, 0x33,
},
};
static const u8 invert[63][32] = {
{
0x95, 0xb2, 0xa8, 0xe3, 0xac, 0xcf, 0x27, 0x3e, 0x1c, 0xa3, 0xcf, 0x7a, 0x20, 0xb4, 0x52, 0x83,
0x0e, 0x21, 0x2d, 0xfe, 0x6f, 0x2e, 0x38, 0x13, 0x01, 0x2e, 0xa0, 0x58, 0x58, 0x6d, 0x4a, 0x6f,
},
{
0x63, 0x26, 0x5c, 0xd2, 0x9a, 0xc6, 0x8c, 0x5d, 0xc2, 0x0d, 0xba, 0x4f, 0x79, 0x88, 0xd1, 0x15,
0x64, 0x55, 0x90, 0x7b, 0x76, 0x2d, 0x60, 0x04, 0x92, 0x77, 0x18, 0xd0, 0xba, 0x7f, 0xee, 0x3a,
},
{
0x57, 0xc1, 0x0b, 0x23, 0x06, 0x57, 0x0c, 0xde, 0xa1, 0xa5, 0x8d, 0xc6, 0x8e, 0xbd, 0x9e, 0x09,
0xe5, 0xed, 0xe3, 0xfb, 0xb1, 0xa0, 0xda, 0x73, 0xfc, 0x3e, 0x5e, 0x6d, 0x38, 0x36, 0x26, 0xec,
},
{
0x8e, 0xe5, 0x30, 0x36, 0x9e, 0x30, 0x82, 0x02, 0xf6, 0x7c, 0x06, 0x71, 0xbb, 0x6e, 0x09, 0x68,
0x16, 0xca, 0x10, 0x32, 0x90, 0xcc, 0x7a, 0x99, 0x18, 0x70, 0xe6, 0xe7, 0x3a, 0x78, 0x86, 0xe6,
},
{
0x18, 0x98, 0x14, 0xa7, 0xb7, 0x1f, 0x24, 0xed, 0xd0, 0xfc, 0x71, 0xa0, 0x7e, 0xef, 0xdd, 0xe2,
0xa2, 0xf8, 0x2a, 0xc2, 0x5d, 0x94, 0x03, 0x13, 0x29, 0x39, 0x86, 0xed, 0x08, 0x99, 0x83, 0xab,
},
{
0xcd, 0x22, 0xa0, 0xbc, 0xea, 0xe7, 0xde, 0xca, 0x0c, 0x72, 0xbd, 0xf7, 0x40, 0x46, 0x92, 0xc5,
0xa4, 0xf3, 0x48, 0x9a, 0x8f, 0x52, 0xab, 0x19, 0x07, 0x98, 0xae, 0x9b, 0xe7, 0xfc, 0xbd, 0x05,
},
{
0xd2, 0xce, 0x28, 0x79, 0x3f, 0xdd, 0xa1, 0x1c, 0x21, 0xe4, 0xeb, 0x54, 0x85, 0x5c, 0x9d, 0x64,
0xd5, 0x5b, 0xb6, 0x06, 0x43, 0xcc, 0x80, 0x8b, 0xe3, 0xdb, 0x26, 0xf5, 0x7e, 0x5f, 0x81, 0x9d,
},
{
0x54, 0x42, 0xe9, 0x30, 0xd2, 0x2c, 0xba, 0x16, 0xa7, 0x99, 0x28, 0xe7, 0x54, 0x61, 0xee, 0x17,
0xf0, 0x70, 0x34, 0xe2, 0xe7, 0x66, 0x16, 0x00, 0x95, 0x7b, 0xbd, 0xd8, 0x07, 0xab, 0xa9, 0x5b,
},
{
0xe7, 0x58, 0x21, 0x24, 0x0e, 0x32, 0xbd, 0x6b, 0xcb, 0xa6, 0xd9, 0x91, 0xd7, 0xfd, 0xe4, 0x4c,
0x58, 0xd6, 0x06, 0x11, 0x02, 0x90, 0xe5, 0x1d, 0x91, 0x2f, 0x0f, 0x43, 0xe3, 0xc7, 0x66, 0xd8,
},
{
0x45, 0x65, 0x5e, 0x17, 0xe1, 0x00, 0xfd, 0x42, 0x30, 0x25, 0x0e, 0xa5, 0x26, 0x8a, 0x17, 0xfe,
0xd0, 0xa2, 0xff, 0x7a, 0x09, 0xd3, 0x5a, 0xb4, 0x71, 0x84, 0x29, 0x03, 0x71, 0x70, 0x9b, 0x6e,
},
{
0xc7, 0x2d, 0xe6, 0xef, 0xba, 0x0b, 0x97, 0x9a, 0x91, 0xf2, 0xda, 0x26, 0x62, 0xe5, 0xbe, 0x5d,
0xc5, 0x5d, 0x71, 0xc1, 0xb7, 0x3f, 0xb3, 0xb8, 0x74, 0xd0, 0x0c, 0x03, 0x74, 0xc0, 0x0c, 0xe4,
},
{
0x56, 0x38, 0x1e, 0x31, 0xca, 0x3b, 0xb5, 0xc4, 0xff, 0x5a, 0x9e, 0x86, 0xfe, 0x98, 0x0c, 0x27,
0x23, 0x2c, 0xa0, 0x76, 0x6f, 0xae, 0xf3, 0xde, 0x71, 0x40, 0x0c, 0xdc, 0x41, 0xf9, 0x89, 0x99,
},
{
0x2c, 0x27, 0xed, 0x69, 0x50, 0x53, 0xc5, 0x97, 0xf4, 0x88, 0x9a, 0x2b, 0xce, 0x8a, 0xc5, 0xfb,
0x0d, 0xbc, 0x6f, 0x9c, 0x84, 0x30, 0xf3, 0xcb, 0xc1, 0x30, 0xa4, 0xb5, 0x46, 0xd4, 0xcb, 0xea,
},
{
0xb7, 0xf0, 0x86, 0x66, 0xd3, 0x55, 0x64, 0xc9, 0x1b, 0x9b, 0x3d, 0x79, 0x13, 0x0a, 0x3e, 0xa1,
0xcf, 0x54, 0x17, 0x77, 0xeb, 0x32, 0x1c, 0x47, 0x7d, 0xf0, 0xb4, 0x11, 0x3d, 0xd7, 0xef, 0x04,
},
{
0xf7, 0x7e, 0x71, 0xb6, 0x5e, 0xed, 0xf3, 0xfb, 0x56, 0x82, 0x22, 0x61, 0x29, 0xa2, 0x5d, 0xc6,
0xcd, 0x03, 0x47, 0xc7, 0xcc, 0xe4, 0xf2, 0xa4, 0x3f, 0xed, 0x36, 0xae, 0xa7, 0x30, 0x84, 0x22,
},
{
0x13, 0x70, 0xe7, 0x97, 0x14, 0xfa, 0xa9, 0xb7, 0xd5, 0xa1, 0xa4, 0xfd, 0xe8, 0x0c, 0x92, 0xcf,
0xc4, 0xdc, 0x5d, 0xb9, 0xa4, 0xa2, 0x16, 0xf8, 0x67, 0xdc, 0x12, 0x47, 0xb7, 0x75, 0xfd, 0x3c,
},
{
0x29, 0xaa, 0xdd, 0xb5, 0xdc, 0x7f, 0xce, 0xad, 0x02, 0x65, 0x27, 0x5e, 0xa5, 0x5d, 0x23, 0x0f,
0xa7, 0x51, 0x4d, 0xf2, 0x7d, 0x2a, 0x31, 0xbf, 0x32, 0x3b, 0x80, 0xe3, 0xda, 0x56, 0xdb, 0xfc,
},
{
0x70, 0xd0, 0x50, 0x6d, 0xf2, 0xb3, 0x6f, 0xc1, 0x9a, 0x98, 0x02, 0x87, 0xb5, 0x31, 0x3d, 0x19,
0xaa, 0xf4, 0xd2, 0xd4, 0x48, 0xb1, 0x08, 0x06, 0x98, 0x39, 0x00, 0x06, 0x20, 0xe5, 0x0c, 0xe1,
},
{
0xe6, 0xaf, 0x94, 0xa0, 0xdf, 0xc3, 0x6b, 0xb4, 0xcf, 0x78, 0xc0, 0xe8, 0x56, 0xdc, 0xac, 0xbb,
0x5e, 0x9e, 0xda, 0x90, 0x1e, 0x7f, 0x44, 0x06, 0xe0, 0x00, 0x6a, 0xd9, 0xd1, 0xf9, 0x56, 0xac,
},
{
0x15, 0xa2, 0x90, 0x13, 0x4f, 0xa0, 0x9d, 0x0d, 0x9c, 0xf8, 0xc9, 0x20, 0x1c, 0x8e, 0x68, 0xcb,
0x1f, 0x75, 0xb3, 0xb2, 0x14, 0xff, 0x19, 0x20, 0x5f, 0x30, 0xb1, 0x05, 0x36, 0x7c, 0xa2, 0xed,
},
{
0x9a, 0xb2, 0xf5, 0xfd, 0x04, 0x3e, 0x6b, 0x4a, 0x1d, 0x3a, 0x63, 0x96, 0x00, 0xad, 0x6c, 0x7c,
0x4f, 0xaf, 0x4d, 0xb5, 0x03, 0x4a, 0xf7, 0x28, 0x7f, 0x1f, 0x38, 0xad, 0xfd, 0xc7, 0x4b, 0x7f,
},
{
0xf4, 0x5a, 0x9f, 0xf6, 0xd0, 0x1a, 0x23, 0x76, 0xee, 0x15, 0x10, 0x2c, 0x30, 0xbd, 0x45, 0xfc,
0x65, 0x60, 0x20, 0xc5, 0x9b, 0xb4, 0x42, 0x83, 0xe9, 0x03, 0xd5, 0xec, 0xba, 0xb2, 0x3b, 0xb8,
},
{
0xf4, 0x1b, 0xc1, 0x73, 0x1a, 0x6c, 0x88, 0xfd, 0xc2, 0xfb, 0xe8, 0x7e, 0xcb, 0x8a, 0x0e, 0x0e,
0x6a, 0x13, 0x54, 0xb0, 0x7b, 0xb8, 0x68, 0x90, 0x21, 0x38, 0x4e, 0x1f, 0x86, 0x51, 0x14, 0x2c,
},
{
0x6c, 0xd3, 0xc3, 0x8f, 0x06, 0x45, 0xec, 0x65, 0x87, 0x02, 0x3d, 0x89, 0x61, 0xde, 0x80, 0x42,
0xf6, 0xe0, 0x8d, 0x91, 0xf0, 0x3a, 0x7a, 0x66, 0xba, 0x1c, 0xc7, 0xb6, 0x3d, 0xc4, 0x7f, 0x91,
},
{
0x53, 0xf6, 0x90, 0x34, 0x88, 0x3e, 0xb7, 0xef, 0x56, 0x39, 0x6e, 0x1f, 0x48, 0x14, 0xe4, 0x09,
0xc6, 0xea, 0xc4, 0xd9, 0xed, 0x2e, 0x2e, 0x33, 0x03, 0x00, 0xb9, 0xac, 0x22, 0x65, 0xe9, 0x1b,
},
{
0x55, 0x78, 0x89, 0x36, 0xa0, 0x07, 0xa6, 0x99, 0xbf, 0x7c, 0xb5, 0xbd, 0xb6, 0x1e, 0xc3, 0x58,
0xb3, 0x0f, 0x78, 0x64, 0x74, 0x77, 0x00, 0x50, 0x2e, 0x4c, 0x6a, 0xa1, 0xe8, 0x93, 0x89, 0x5d,
},
{
0x09, 0xf8, 0xdd, 0xe0, 0x42, 0xa4, 0x2e, 0x9d, 0xff, 0x0e, 0x70, 0x73, 0x9c, 0x87, 0xa0, 0x81,
0x4d, 0xb1, 0xc3, 0xf3, 0xff, 0x96, 0x3b, 0x2a, 0xdf, 0x6d, 0x97, 0xba, 0x06, 0xa7, 0x7e, 0x0a,
},
{
0x1f, 0x46, 0xb4, 0x72, 0x14, 0x5b, 0x85, 0x01, 0x83, 0xcc, 0x24, 0x17, 0xc2, 0x07, 0xda, 0x60,
0x6c, 0xab, 0xfa, 0xe5, 0xd9, 0xb4, 0xf0, 0x3f, 0xca, 0xf1, 0x30, 0x8d, 0xd2, 0x4e, 0xe3, 0xb4,
},
{
0x4f, 0xb3, 0x0d, 0x98, 0x38, 0x70, 0x28, 0xa2, 0xca, 0x5d, 0x2c, 0xdf, 0x1f, 0xce, 0xff, 0xcc,
0x75, 0x49, 0xa0, 0xef, 0x54, 0xd9, 0x32, 0x1b, 0x17, 0xb6, 0x7e, 0x7a, 0xa6, 0x5f, 0x7a, 0xff,
},
{
0x81, 0x6b, 0x06, 0x73, 0x5b, 0x32, 0x0d, 0x37, 0xb4, 0x50, 0x63, 0x52, 0x25, 0x72, 0x5c, 0xf5,
0x5d, 0x58, 0xa6, 0xbf, 0x08, 0xcc, 0x1d, 0x70, 0x2d, 0x12, 0x5d, 0xd7, 0xbd, 0xca, 0xe7, 0x10,
},
{
0x8f, 0xfc, 0x57, 0x17, 0xce, 0x47, 0x10, 0x79, 0xae, 0x66, 0xa5, 0xcc, 0x98, 0x0b, 0x77, 0xe8,
0xa2, 0x6e, 0xc1, 0x0d, 0x03, 0xe3, 0x5b, 0xed, 0x38, 0x0e, 0x31, 0x2d, 0x19, 0x4d, 0xd6, 0x2a,
},
{
0xc6, 0x9d, 0x2d, 0x0b, 0xad, 0x6d, 0x0c, 0x61, 0x2d, 0x62, 0xe4, 0xce, 0x73, 0x47, 0x72, 0x20,
0x0c, 0x8e, 0x8f, 0xe9, 0xe7, 0x67, 0x66, 0x2e, 0x17, 0x54, 0xec, 0x15, 0x3e, 0x1b, 0xf3, 0x04,
},
{
0xf4, 0xee, 0x03, 0x30, 0x2e, 0x1e, 0xa4, 0xb1, 0x86, 0x6d, 0xc3, 0x54, 0xf3, 0xc5, 0x61, 0xa6,
0xb9, 0x28, 0x29, 0x11, 0x91, 0xcb, 0xbd, 0xc9, 0x77, 0x62, 0x09, 0x8c, 0xa4, 0x40, 0x84, 0x97,
},
{
0xff, 0x98, 0x9b, 0xbc, 0xc2, 0xf0, 0xf8, 0x7f, 0x5c, 0x86, 0x74, 0x33, 0xee, 0x42, 0x6e, 0xab,
0xd4, 0xd2, 0x1a, 0x0d, 0x41, 0x2d, 0xac, 0xa1, 0x3e, 0x56, 0xed, 0x4b, 0x27, 0x5a, 0x65, 0xe4,
},
{
0x2b, 0xb1, 0xe3, 0x64, 0xaa, 0x32, 0x17, 0x57, 0x7c, 0x67, 0xb8, 0x6b, 0x00, 0x53, 0xbe, 0x3e,
0xec, 0xd1, 0x1b, 0xc4, 0xc3, 0x8d, 0xe6, 0x19, 0xe8, 0x3a, 0x25, 0x98, 0x4e, 0xe9, 0xd4, 0x60,
},
{
0xa6, 0x2e, 0xb3, 0xc8, 0xcd, 0xc9, 0xc2, 0x8e, 0xe1, 0xf0, 0x8f, 0x96, 0x8e, 0xc6, 0x37, 0x11,
0xbc, 0x6c, 0x0c, 0xf6, 0xb6, 0x83, 0x38, 0x96, 0x7a, 0x74, 0x5a, 0xa7, 0xe1, 0x11, 0x8d, 0x8b,
},
{
0x90, 0xf2, 0x4d, 0xbd, 0x83, 0x39, 0xe6, 0x54, 0xf6, 0x75, 0xf6, 0x2c, 0x28, 0x3d, 0xd1, 0xcf,
0xe1, 0xfb, 0x9f, 0x97, 0x19, 0xca, 0x4d, 0x2c, 0x38, 0x3d, 0x36, 0xed, 0x19, 0xe9, 0x4a, 0x0b,
},
{
0x1a, 0x61, 0xb8, 0x19, 0x59, 0x16, 0x74, 0xec, 0xdb, 0x7b, 0xeb, 0xd6, 0xae, 0xcd, 0xe9, 0x55,
0xdb, 0x45, 0xdc, 0xf2, 0x35, 0x84, 0xe9, 0xe6, 0x17, 0x48, 0xac, 0x38, 0x05, 0x21, 0x2c, 0x8e,
},
{
0x41, 0xac, 0x17, 0x42, 0xcc, 0x17, 0x10, 0x02, 0x07, 0x7e, 0xfc, 0x4d, 0x77, 0x06, 0x70, 0xcb,
0x40, 0x8b, 0x47, 0x47, 0x07, 0x29, 0x82, 0xca, 0x93, 0x69, 0x2f, 0x3a, 0x64, 0xc6, 0xcb, 0x23,
},
{
0xa2, 0xcb, 0x2d, 0x02, 0x5d, 0x30, 0x9f, 0x32, 0xf5, 0xc5, 0x13, 0xff, 0xfc, 0xe2, 0xfb, 0x26,
0x3b, 0x3b, 0xaf, 0xa4, 0x37, 0x6d, 0x45, 0xbf, 0xdb, 0xb9, 0xee, 0xec, 0x92, 0xa5, 0x1d, 0x0d,
},
{
0xa4, 0xef, 0x08, 0xb7, 0xb4, 0x68, 0x74, 0x93, 0xb2, 0xda, 0xba, 0xe9, 0x05, 0xf5, 0x09, 0xb6,
0x53, 0xdd, 0x17, 0x60, 0xbb, 0x1e, 0xb0, 0x71, 0xd8, 0x47, 0x85, 0x02, 0x13, 0xbe, 0xa2, 0x67,
},
{
0x31, 0x50, 0x90, 0xb0, 0x83, 0x4a, 0xcf, 0x3f, 0xbe, 0x88, 0x90, 0x4b, 0xe1, 0x9f, 0xe6, 0xd0,
0xfd, 0x01, 0x8e, 0xfc, 0xc0, 0x8c, 0x2f, 0x9b, 0x48, 0x70, 0x9d, 0x4e, 0x22, 0x21, 0x07, 0x09,
},
{
0x15, 0x9f, 0x37, 0x45, 0x52, 0x99, 0x6e, 0xe9, 0x1a, 0x25, 0x56, 0x0b, 0x19, 0xf1, 0xca, 0x9f,
0x29, 0xe5, 0x23, 0xa6, 0x0b, 0x94, 0x0a, 0xe3, 0x74, 0xaa, 0xd5, 0x35, 0xaf, 0x6e, 0xb2, 0x24,
},
{
0x68, 0xab, 0xa6, 0x8b, 0x5f, 0xc7, 0x93, 0x1a, 0x06, 0x51, 0x2c, 0x3b, 0xad, 0x44, 0x6b, 0x69,
0x1a, 0x1d, 0x41, 0xca, 0x8e, 0x59, 0x2c, 0x83, 0x71, 0x48, 0x8c, 0xaf, 0x50, 0x85, 0x00, 0xf3,
},
{
0xe2, 0xa6, 0x38, 0x93, 0xca, 0xe3, 0xd0, 0x36, 0xf4, 0xe9, 0x53, 0xfb, 0xa0, 0xd0, 0x13, 0xd3,
0x2b, 0x7d, 0x46, 0xc8, 0x8b, 0xc7, 0x8c, 0xca, 0x59, 0xec, 0x66, 0x17, 0x70, 0xbb, 0xf9, 0x92,
},
{
0x89, 0xca, 0x92, 0x19, 0x01, 0xb8, 0x4b, 0x97, 0x06, 0x1a, 0x12, 0x91, 0x72, 0x11, 0xeb, 0x12,
0x8b, 0x12, 0xd9, 0xdc, 0xc9, 0xb2, 0x37, 0xf8, 0x3e, 0x02, 0x03, 0xbe, 0x45, 0x45, 0xc9, 0x42,
},
{
0x45, 0x2c, 0x80, 0xe1, 0x3a, 0x0a, 0xdf, 0xa3, 0xd2, 0x4a, 0x23, 0x0d, 0x47, 0x0d, 0x49, 0xad,
0xdf, 0xb0, 0x42, 0xdf, 0x87, 0x85, 0xa6, 0x8f, 0x9f, 0x7e, 0x9b, 0xa4, 0x42, 0x64, 0xcb, 0xfb,
},
{
0xc7, 0x39, 0x26, 0xb1, 0x90, 0x4d, 0xc1, 0x7a, 0xea, 0x31, 0x1b, 0xae, 0x1a, 0x5c, 0x1f, 0x4f,
0x44, 0x2f, 0x87, 0x08, 0x5d, 0xa6, 0x74, 0xfd, 0xab, 0xb2, 0x4b, 0x01, 0xed, 0xd5, 0x4c, 0xe6,
},
{
0x2a, 0xef, 0xfa, 0x25, 0x3c, 0xd2, 0xc8, 0x08, 0x9c, 0x33, 0x3c, 0x47, 0xb3, 0xb5, 0x44, 0x34,
0x97, 0xee, 0xe8, 0x52, 0x1c, 0x15, 0xb3, 0xe0, 0xda, 0xef, 0x77, 0xde, 0x15, 0x39, 0x4b, 0x38,
},
{
0x8a, 0x3a, 0x59, 0x61, 0x9d, 0x3e, 0x9b, 0x38, 0xc9, 0x84, 0x80, 0xaf, 0xb4, 0x37, 0x8a, 0x67,
0x47, 0xc9, 0x6c, 0x72, 0xef, 0x39, 0x50, 0x28, 0x6c, 0x8f, 0xad, 0x09, 0x75, 0x26, 0xc9, 0xa9,
},
{
0x27, 0x1e, 0x8b, 0xf6, 0x6b, 0x56, 0x5d, 0x17, 0x58, 0xac, 0xdf, 0x27, 0xd9, 0x3e, 0x5b, 0xdd,
0xaf, 0xbc, 0xb7, 0xf9, 0x76, 0x3b, 0x40, 0x06, 0xbc, 0x6e, 0xec, 0xaa, 0xb2, 0xdc, 0x9a, 0x0c,
},
{
0x09, 0x14, 0xef, 0x19, 0xc7, 0x7d, 0xc8, 0xa3, 0xd0, 0xaa, 0x7f, 0x09, 0x18, 0xaf, 0xd3, 0xde,
0xbf, 0x05, 0xfc, 0xf9, 0xeb, 0xc0, 0x8e, 0xcf, 0xc7, 0x4c, 0x2f, 0x3f, 0xd4, 0x51, 0x41, 0xb2,
},
{
0xb7, 0x33, 0xf3, 0x72, 0x6d, 0x12, 0xc1, 0x5c, 0x5d, 0x81, 0xb3, 0x63, 0x81, 0x50, 0x81, 0xc0,
0x4a, 0xea, 0x18, 0x7c, 0xa6, 0x2d, 0x23, 0xba, 0x4b, 0xb9, 0x31, 0xd9, 0xab, 0x20, 0x60, 0x77,
},
{
0xbb, 0x1c, 0x50, 0x2d, 0xdc, 0x18, 0x27, 0x98, 0x60, 0xde, 0x17, 0xd9, 0x17, 0x3c, 0xd5, 0x98,
0xc3, 0x12, 0xfd, 0x8b, 0x25, 0x1e, 0xa5, 0xc1, 0xa8, 0xef, 0xec, 0x05, 0x3e, 0xfc, 0xd1, 0xfc,
},
{
0xe6, 0x3b, 0x9f, 0x33, 0x85, 0xeb, 0x91, 0xd0, 0xad, 0x2f, 0xc2, 0x96, 0x61, 0x64, 0xbc, 0x12,
0x15, 0x79, 0x65, 0x93, 0xc2, 0x63, 0xa3, 0x27, 0x88, 0x60, 0x39, 0x35, 0x21, 0x05, 0xe9, 0x49,
},
{
0x9b, 0x68, 0xe7, 0xc8, 0xea, 0x0e, 0x5c, 0xa4, 0x03, 0x3a, 0x4e, 0x31, 0xb1, 0x92, 0xad, 0x9d,
0x7e, 0xb5, 0x93, 0x81, 0xdd, 0x7a, 0xe9, 0xa1, 0x69, 0x28, 0x6a, 0xaf, 0x48, 0x05, 0x94, 0xc0,
},
{
0x66, 0x3d, 0x87, 0xc1, 0x48, 0x9d, 0xdf, 0x99, 0x25, 0xd7, 0xb0, 0xfa, 0x03, 0x8b, 0x62, 0x60,
0xc5, 0x07, 0x3f, 0xa2, 0xc8, 0xbd, 0x70, 0xdb, 0x40, 0x6c, 0x65, 0xbf, 0x15, 0xfc, 0x1e, 0xc9,
},
{
0x38, 0x9c, 0x1a, 0x5b, 0x4f, 0x84, 0xca, 0xe1, 0x30, 0x6a, 0xf0, 0xb6, 0xf1, 0x61, 0xd3, 0xb0,
0xa6, 0x6d, 0x0d, 0x11, 0x03, 0xe0, 0xcb, 0x9f, 0xbe, 0x7e, 0xc2, 0x7a, 0x53, 0x9d, 0x39, 0xcb,
},
{
0xf3, 0x47, 0x4a, 0x37, 0xcd, 0x19, 0x27, 0x0f, 0xfb, 0x3f, 0xcb, 0x81, 0x1e, 0x0f, 0xfd, 0x1f,
0x2e, 0x8d, 0xff, 0xe9, 0x52, 0x8b, 0x8e, 0x52, 0x3c, 0x82, 0xe6, 0x44, 0xf6, 0x92, 0xd4, 0xd4,
},
{
0x3a, 0xe8, 0x4d, 0xcc, 0x4a, 0x0e, 0xaa, 0xf6, 0x32, 0x88, 0x4c, 0xee, 0xaa, 0x9c, 0xeb, 0x59,
0xb5, 0xb8, 0x06, 0x89, 0x49, 0xc9, 0xa6, 0xf7, 0xa6, 0x14, 0x44, 0x55, 0x5e, 0x3e, 0x86, 0x08,
},
{
0xca, 0x3d, 0x95, 0x21, 0xf3, 0xbb, 0x78, 0x29, 0x6a, 0x38, 0xd3, 0xe4, 0x48, 0x98, 0x6f, 0x0e,
0xaf, 0x46, 0xa5, 0x02, 0xdd, 0xfb, 0x52, 0x42, 0x9b, 0x69, 0x97, 0xe6, 0x68, 0x21, 0x0d, 0x69,
},
{
0x3a, 0x8a, 0x14, 0x6e, 0xa2, 0x24, 0x8f, 0x89, 0x5e, 0x99, 0x8a, 0x5b, 0x90, 0xb1, 0xf3, 0x64,
0x4d, 0x10, 0xef, 0x45, 0xa9, 0xfb, 0xbb, 0xc0, 0xf5, 0x66, 0xdf, 0x15, 0xae, 0xd0, 0xd9, 0x56,
},
{
0x62, 0x50, 0x52, 0xb5, 0xb9, 0x76, 0xa7, 0xcb, 0xe6, 0xf7, 0x3a, 0x9f, 0xa4, 0x1e, 0x0a, 0x4d,
0x88, 0xa4, 0x1c, 0xea, 0x11, 0x8c, 0xfb, 0xbe, 0x70, 0x62, 0xec, 0x4e, 0x00, 0x56, 0x0e, 0xa9,
},
};

6
src/southbridge/intel/bd82x6x/Makefile.inc
View File

@ -45,10 +45,14 @@ smm-$(CONFIG_SPI_FLASH_SMM) += ../common/spi.c
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c finalize.c pch.c
romstage-y += early_usb.c early_smbus.c early_me.c me_status.c gpio.c
romstage-y += early_usb.c early_smbus.c me_status.c gpio.c
romstage-y += reset.c
romstage-y += early_spi.c early_pch.c
romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += early_me.c
romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += early_me.c
romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) += early_thermal.c early_pch_native.c early_me_native.c
ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
IFD_BIN_PATH := $(objgenerated)/ifdfake.bin
IFD_SECTIONS := $(addprefix -b ,$(CONFIG_IFD_BIOS_SECTION:"%"=%)) \

272
src/southbridge/intel/bd82x6x/early_me_native.c Normal file
View File

@ -0,0 +1,272 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#include <arch/hlt.h>
#include <arch/io.h>
#include <console/console.h>
#include <delay.h>
#include <device/pci_ids.h>
#include <string.h>
#include "me.h"
#include "pch.h"
static const char *me_ack_values[] = {
[ME_HFS_ACK_NO_DID] = "No DID Ack received",
[ME_HFS_ACK_RESET] = "Non-power cycle reset",
[ME_HFS_ACK_PWR_CYCLE] = "Power cycle reset",
[ME_HFS_ACK_S3] = "Go to S3",
[ME_HFS_ACK_S4] = "Go to S4",
[ME_HFS_ACK_S5] = "Go to S5",
[ME_HFS_ACK_GBL_RESET] = "Global Reset",
[ME_HFS_ACK_CONTINUE] = "Continue to boot"
};
static inline void pci_read_dword_ptr(void *ptr, int offset)
{
u32 dword = pci_read_config32(PCH_ME_DEV, offset);
memcpy(ptr, &dword, sizeof(dword));
}
static inline void pci_write_dword_ptr(void *ptr, int offset)
{
u32 dword = 0;
memcpy(&dword, ptr, sizeof(dword));
pci_write_config32(PCH_ME_DEV, offset, dword);
}
void intel_early_me_status(void)
{
struct me_hfs hfs;
struct me_gmes gmes;
pci_read_dword_ptr(&hfs, PCI_ME_HFS);
pci_read_dword_ptr(&gmes, PCI_ME_GMES);
intel_me_status(&hfs, &gmes);
}
int intel_early_me_init(void)
{
int count;
struct me_uma uma;
struct me_hfs hfs;
printk(BIOS_INFO, "Intel ME early init\n");
/* Wait for ME UMA SIZE VALID bit to be set */
for (count = ME_RETRY; count > 0; --count) {
pci_read_dword_ptr(&uma, PCI_ME_UMA);
if (uma.valid)
break;
udelay(ME_DELAY);
}
if (!count) {
printk(BIOS_ERR, "ERROR: ME is not ready!\n");
return -1;
}
/* Check for valid firmware */
pci_read_dword_ptr(&hfs, PCI_ME_HFS);
if (hfs.fpt_bad) {
printk(BIOS_WARNING, "WARNING: ME has bad firmware\n");
return -1;
}
printk(BIOS_INFO, "Intel ME firmware is ready\n");
return 0;
}
int intel_early_me_uma_size(void)
{
struct me_uma uma;
pci_read_dword_ptr(&uma, PCI_ME_UMA);
if (uma.valid) {
printk(BIOS_DEBUG, "ME: Requested %uMB UMA\n", uma.size);
return uma.size;
}
printk(BIOS_DEBUG, "ME: Invalid UMA size\n");
return 0;
}
static inline void set_global_reset(int enable)
{
u32 etr3 = pci_read_config32(PCH_LPC_DEV, ETR3);
/* Clear CF9 Without Resume Well Reset Enable */
etr3 &= ~ETR3_CWORWRE;
/* CF9GR indicates a Global Reset */
if (enable)
etr3 |= ETR3_CF9GR;
else
etr3 &= ~ETR3_CF9GR;
pci_write_config32(PCH_LPC_DEV, ETR3, etr3);
}
int intel_early_me_init_done(u8 status)
{
u8 reset, errorcode, opmode;
u16 reg16;
u32 mebase_l, mebase_h;
u32 millisec;
u32 hfs, me_fws2;
struct me_did did = {
.init_done = ME_INIT_DONE,
.status = status
};
u32 meDID;
hfs = (pci_read_config32(PCI_DEV(0, 0x16, 0), PCI_ME_HFS) & 0xff000) >> 12;
opmode = (hfs & 0xf0) >> 4;
errorcode = hfs & 0xf;
if (opmode != ME_HFS_MODE_NORMAL) {
printk(BIOS_NOTICE, "ME: Wrong mode : %d\n", opmode);
//return 0;
}
if (errorcode) {
printk(BIOS_NOTICE, "ME: HFS error : %d\n", errorcode);
//return 0;
}
me_fws2 = pci_read_config32(PCI_DEV(0, 0x16, 0), 0x48);
printk(BIOS_NOTICE, "ME: FWS2: 0x%x\n", me_fws2);
printk(BIOS_NOTICE, "ME: Bist in progress: 0x%x\n", me_fws2 & 0x1);
printk(BIOS_NOTICE, "ME: ICC Status : 0x%x\n", (me_fws2 & 0x6) >> 1);
printk(BIOS_NOTICE, "ME: Invoke MEBx : 0x%x\n", (me_fws2 & 0x8) >> 3);
printk(BIOS_NOTICE, "ME: CPU replaced : 0x%x\n", (me_fws2 & 0x10) >> 4);
printk(BIOS_NOTICE, "ME: MBP ready : 0x%x\n", (me_fws2 & 0x20) >> 5);
printk(BIOS_NOTICE, "ME: MFS failure : 0x%x\n", (me_fws2 & 0x40) >> 6);
printk(BIOS_NOTICE, "ME: Warm reset req : 0x%x\n", (me_fws2 & 0x80) >> 7);
printk(BIOS_NOTICE, "ME: CPU repl valid : 0x%x\n", (me_fws2 & 0x100) >> 8);
printk(BIOS_NOTICE, "ME: (Reserved) : 0x%x\n", (me_fws2 & 0x600) >> 9);
printk(BIOS_NOTICE, "ME: FW update req : 0x%x\n", (me_fws2 & 0x800) >> 11);
printk(BIOS_NOTICE, "ME: (Reserved) : 0x%x\n", (me_fws2 & 0xf000) >> 12);
printk(BIOS_NOTICE, "ME: Current state : 0x%x\n", (me_fws2 & 0xff0000) >> 16);
printk(BIOS_NOTICE, "ME: Current PM event: 0x%x\n", (me_fws2 & 0xf000000) >> 24);
printk(BIOS_NOTICE, "ME: Progress code : 0x%x\n", (me_fws2 & 0xf0000000) >> 28);
// Poll cpu replaced for 50ms
millisec = 0;
while ((((me_fws2 & 0x100) >> 8) == 0) && millisec < 50) {
udelay(1000);
me_fws2 = pci_read_config32(PCI_DEV(0, 0x16, 0), 0x48);
millisec++;
}
if (millisec >= 50 || ((me_fws2 & 0x100) >> 8) == 0x0) {
printk(BIOS_NOTICE, "Waited long enough, or CPU was not replaced, continue...\n");
} else if ((me_fws2 & 0x100) == 0x100) {
if ((me_fws2 & 0x80) == 0x80) {
printk(BIOS_NOTICE, "CPU was replaced & warm reset required...\n");
reg16 = pcie_read_config16(PCI_DEV(0, 31, 0), 0xa2) & ~0x80;
pcie_write_config16(PCI_DEV(0, 31, 0), 0xa2, reg16);
set_global_reset(0);
outb(0x6, 0xcf9);
hlt();
}
if (((me_fws2 & 0x10) == 0x10) && (me_fws2 & 0x80) == 0x00) {
printk(BIOS_NOTICE, "Full training required\n");
}
}
printk(BIOS_NOTICE, "PASSED! Tell ME that DRAM is ready\n");
/* MEBASE from MESEG_BASE[35:20] */
mebase_l = pci_read_config32(PCI_CPU_DEVICE, PCI_CPU_MEBASE_L);
mebase_h = pci_read_config32(PCI_CPU_DEVICE, PCI_CPU_MEBASE_H) & 0xf;
did.uma_base = (mebase_l >> 20) | (mebase_h << 12);
meDID = did.uma_base | (1 << 28);// | (1 << 23);
pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_ME_H_GS, meDID);
udelay(1100);
/* Must wait for ME acknowledgement */
millisec = 0;
hfs = (pci_read_config32(PCI_DEV(0, 0x16, 0), PCI_ME_HFS) & 0xfe000000) >> 24;
while ((((hfs & 0xf0) >> 4) != ME_HFS_BIOS_DRAM_ACK) && (millisec < 5000)) {
udelay(1000);
hfs = (pci_read_config32(PCI_DEV(0, 0x16, 0), PCI_ME_HFS) & 0xfe000000) >> 24;
millisec++;
}
me_fws2 = pci_read_config32(PCI_DEV(0, 0x16, 0), 0x48);
printk(BIOS_NOTICE, "ME: FWS2: 0x%x\n", me_fws2);
printk(BIOS_NOTICE, "ME: Bist in progress: 0x%x\n", me_fws2 & 0x1);
printk(BIOS_NOTICE, "ME: ICC Status : 0x%x\n", (me_fws2 & 0x6) >> 1);
printk(BIOS_NOTICE, "ME: Invoke MEBx : 0x%x\n", (me_fws2 & 0x8) >> 3);
printk(BIOS_NOTICE, "ME: CPU replaced : 0x%x\n", (me_fws2 & 0x10) >> 4);
printk(BIOS_NOTICE, "ME: MBP ready : 0x%x\n", (me_fws2 & 0x20) >> 5);
printk(BIOS_NOTICE, "ME: MFS failure : 0x%x\n", (me_fws2 & 0x40) >> 6);
printk(BIOS_NOTICE, "ME: Warm reset req : 0x%x\n", (me_fws2 & 0x80) >> 7);
printk(BIOS_NOTICE, "ME: CPU repl valid : 0x%x\n", (me_fws2 & 0x100) >> 8);
printk(BIOS_NOTICE, "ME: (Reserved) : 0x%x\n", (me_fws2 & 0x600) >> 9);
printk(BIOS_NOTICE, "ME: FW update req : 0x%x\n", (me_fws2 & 0x800) >> 11);
printk(BIOS_NOTICE, "ME: (Reserved) : 0x%x\n", (me_fws2 & 0xf000) >> 12);
printk(BIOS_NOTICE, "ME: Current state : 0x%x\n", (me_fws2 & 0xff0000) >> 16);
printk(BIOS_NOTICE, "ME: Current PM event: 0x%x\n", (me_fws2 & 0xf000000) >> 24);
printk(BIOS_NOTICE, "ME: Progress code : 0x%x\n", (me_fws2 & 0xf0000000) >> 28);
/* Return the requested BIOS action */
printk(BIOS_NOTICE, "ME: Requested BIOS Action: %s\n",
me_ack_values[(hfs & 0xe) >> 1]);
reset = inb(0xcf9);
reset &= 0xf1;
switch ((hfs & 0xe) >> 1) {
case ME_HFS_ACK_NO_DID:
case ME_HFS_ACK_CONTINUE:
/* Continue to boot */
return 0;
case ME_HFS_ACK_RESET:
/* Non-power cycle reset */
set_global_reset(0);
reset |= 0x06;
break;
case ME_HFS_ACK_PWR_CYCLE:
/* Power cycle reset */
set_global_reset(0);
reset |= 0x0e;
break;
case ME_HFS_ACK_GBL_RESET:
/* Global reset */
set_global_reset(1);
reset |= 0x0e;
break;
case ME_HFS_ACK_S3:
case ME_HFS_ACK_S4:
case ME_HFS_ACK_S5:
break;
}
/* Perform the requested reset */
if (reset) {
outb(reset, 0xcf9);
hlt();
}
return -1;
}

375
src/southbridge/intel/bd82x6x/early_pch_native.c Normal file
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@ -0,0 +1,375 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Vladimir Serbinenko <phcoder@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <console/console.h>
#include <string.h>
#include <arch/hlt.h>
#include <arch/io.h>
#include <cbmem.h>
#include <arch/cbfs.h>
#include <cbfs.h>
#include <ip_checksum.h>
#include <pc80/mc146818rtc.h>
#include <device/pci_def.h>
#include <delay.h>
#include "pch.h"
/* For DMI bar. */
#include "northbridge/intel/sandybridge/sandybridge.h"
#define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0)
static void
wait_2338 (void)
{
while (read8 (DEFAULT_RCBA | 0x2338) & 1);
}
static u32
read_2338 (u32 edx)
{
u32 ret;
write32 (DEFAULT_RCBA | 0x2330, edx);
write16 (DEFAULT_RCBA | 0x2338, (read16 (DEFAULT_RCBA | 0x2338)
& 0x1ff) | 0x600);
wait_2338 ();
ret = read32 (DEFAULT_RCBA | 0x2334);
wait_2338 ();
read8 (DEFAULT_RCBA | 0x2338);
return ret;
}
static void
write_2338 (u32 edx, u32 val)
{
read_2338 (edx);
write16 (DEFAULT_RCBA | 0x2338, (read16 (DEFAULT_RCBA | 0x2338)
& 0x1ff) | 0x600);
wait_2338 ();
write32 (DEFAULT_RCBA | 0x2334, val);
wait_2338 ();
write16 (DEFAULT_RCBA | 0x2338,
(read16 (DEFAULT_RCBA | 0x2338) & 0x1ff) | 0x600);
read8 (DEFAULT_RCBA | 0x2338);
}
static void
init_dmi (void)
{
int i;
write32 (DEFAULT_DMIBAR | 0x0914,
read32 (DEFAULT_DMIBAR | 0x0914) | 0x80000000);
write32 (DEFAULT_DMIBAR | 0x0934,
read32 (DEFAULT_DMIBAR | 0x0934) | 0x80000000);
for (i = 0; i < 4; i++)
{
write32 (DEFAULT_DMIBAR | 0x0a00 | (i << 4),
read32 (DEFAULT_DMIBAR | 0x0a00 | (i << 4)) & 0xf3ffffff);
write32 (DEFAULT_DMIBAR | 0x0a04 | (i << 4),
read32 (DEFAULT_DMIBAR | 0x0a04 | (i << 4)) | 0x800);
}
write32 (DEFAULT_DMIBAR | 0x0c30, (read32 (DEFAULT_DMIBAR | 0x0c30)
& 0xfffffff) | 0x40000000);
for (i = 0; i < 2; i++)
{
write32 (DEFAULT_DMIBAR | 0x0904 | (i << 5),
read32 (DEFAULT_DMIBAR | 0x0904 | (i << 5)) & 0xfe3fffff);
write32 (DEFAULT_DMIBAR | 0x090c | (i << 5),
read32 (DEFAULT_DMIBAR | 0x090c | (i << 5)) & 0xfff1ffff);
}
write32 (DEFAULT_DMIBAR | 0x090c,
read32 (DEFAULT_DMIBAR | 0x090c) & 0xfe1fffff);
write32 (DEFAULT_DMIBAR | 0x092c,
read32 (DEFAULT_DMIBAR | 0x092c) & 0xfe1fffff);
read32 (DEFAULT_DMIBAR | 0x0904); // !!! = 0x7a1842ec
write32 (DEFAULT_DMIBAR | 0x0904, 0x7a1842ec);
read32 (DEFAULT_DMIBAR | 0x090c); // !!! = 0x00000208
write32 (DEFAULT_DMIBAR | 0x090c, 0x00000128);
read32 (DEFAULT_DMIBAR | 0x0924); // !!! = 0x7a1842ec
write32 (DEFAULT_DMIBAR | 0x0924, 0x7a1842ec);
read32 (DEFAULT_DMIBAR | 0x092c); // !!! = 0x00000208
write32 (DEFAULT_DMIBAR | 0x092c, 0x00000128);
read32 (DEFAULT_DMIBAR | 0x0700); // !!! = 0x46139008
write32 (DEFAULT_DMIBAR | 0x0700, 0x46139008);
read32 (DEFAULT_DMIBAR | 0x0720); // !!! = 0x46139008
write32 (DEFAULT_DMIBAR | 0x0720, 0x46139008);
read32 (DEFAULT_DMIBAR | 0x0c04); // !!! = 0x2e680008
write32 (DEFAULT_DMIBAR | 0x0c04, 0x2e680008);
read32 (DEFAULT_DMIBAR | 0x0904); // !!! = 0x7a1842ec
write32 (DEFAULT_DMIBAR | 0x0904, 0x3a1842ec);
read32 (DEFAULT_DMIBAR | 0x0924); // !!! = 0x7a1842ec
write32 (DEFAULT_DMIBAR | 0x0924, 0x3a1842ec);
read32 (DEFAULT_DMIBAR | 0x0910); // !!! = 0x00006300
write32 (DEFAULT_DMIBAR | 0x0910, 0x00004300);
read32 (DEFAULT_DMIBAR | 0x0930); // !!! = 0x00006300
write32 (DEFAULT_DMIBAR | 0x0930, 0x00004300);
read32 (DEFAULT_DMIBAR | 0x0a00); // !!! = 0x03042010
write32 (DEFAULT_DMIBAR | 0x0a00, 0x03042018);
read32 (DEFAULT_DMIBAR | 0x0a10); // !!! = 0x03042010
write32 (DEFAULT_DMIBAR | 0x0a10, 0x03042018);
read32 (DEFAULT_DMIBAR | 0x0a20); // !!! = 0x03042010
write32 (DEFAULT_DMIBAR | 0x0a20, 0x03042018);
read32 (DEFAULT_DMIBAR | 0x0a30); // !!! = 0x03042010
write32 (DEFAULT_DMIBAR | 0x0a30, 0x03042018);
read32 (DEFAULT_DMIBAR | 0x0c00); // !!! = 0x29700c08
write32 (DEFAULT_DMIBAR | 0x0c00, 0x29700c08);
read32 (DEFAULT_DMIBAR | 0x0a04); // !!! = 0x0c0708f0
write32 (DEFAULT_DMIBAR | 0x0a04, 0x0c0718f0);
read32 (DEFAULT_DMIBAR | 0x0a14); // !!! = 0x0c0708f0
write32 (DEFAULT_DMIBAR | 0x0a14, 0x0c0718f0);
read32 (DEFAULT_DMIBAR | 0x0a24); // !!! = 0x0c0708f0
write32 (DEFAULT_DMIBAR | 0x0a24, 0x0c0718f0);
read32 (DEFAULT_DMIBAR | 0x0a34); // !!! = 0x0c0708f0
write32 (DEFAULT_DMIBAR | 0x0a34, 0x0c0718f0);
read32 (DEFAULT_DMIBAR | 0x0900); // !!! = 0x50000000
write32 (DEFAULT_DMIBAR | 0x0900, 0x50000000);
read32 (DEFAULT_DMIBAR | 0x0920); // !!! = 0x50000000
write32 (DEFAULT_DMIBAR | 0x0920, 0x50000000);
read32 (DEFAULT_DMIBAR | 0x0908); // !!! = 0x51ffffff
write32 (DEFAULT_DMIBAR | 0x0908, 0x51ffffff);
read32 (DEFAULT_DMIBAR | 0x0928); // !!! = 0x51ffffff
write32 (DEFAULT_DMIBAR | 0x0928, 0x51ffffff);
read32 (DEFAULT_DMIBAR | 0x0a00); // !!! = 0x03042018
write32 (DEFAULT_DMIBAR | 0x0a00, 0x03042018);
read32 (DEFAULT_DMIBAR | 0x0a10); // !!! = 0x03042018
write32 (DEFAULT_DMIBAR | 0x0a10, 0x03042018);
read32 (DEFAULT_DMIBAR | 0x0a20); // !!! = 0x03042018
write32 (DEFAULT_DMIBAR | 0x0a20, 0x03042018);
read32 (DEFAULT_DMIBAR | 0x0a30); // !!! = 0x03042018
write32 (DEFAULT_DMIBAR | 0x0a30, 0x03042018);
read32 (DEFAULT_DMIBAR | 0x0700); // !!! = 0x46139008
write32 (DEFAULT_DMIBAR | 0x0700, 0x46139008);
read32 (DEFAULT_DMIBAR | 0x0720); // !!! = 0x46139008
write32 (DEFAULT_DMIBAR | 0x0720, 0x46139008);
read32 (DEFAULT_DMIBAR | 0x0904); // !!! = 0x3a1842ec
write32 (DEFAULT_DMIBAR | 0x0904, 0x3a1846ec);
read32 (DEFAULT_DMIBAR | 0x0924); // !!! = 0x3a1842ec
write32 (DEFAULT_DMIBAR | 0x0924, 0x3a1846ec);
read32 (DEFAULT_DMIBAR | 0x0a00); // !!! = 0x03042018
write32 (DEFAULT_DMIBAR | 0x0a00, 0x03042018);
read32 (DEFAULT_DMIBAR | 0x0a10); // !!! = 0x03042018
write32 (DEFAULT_DMIBAR | 0x0a10, 0x03042018);
read32 (DEFAULT_DMIBAR | 0x0a20); // !!! = 0x03042018
write32 (DEFAULT_DMIBAR | 0x0a20, 0x03042018);
read32 (DEFAULT_DMIBAR | 0x0a30); // !!! = 0x03042018
write32 (DEFAULT_DMIBAR | 0x0a30, 0x03042018);
read32 (DEFAULT_DMIBAR | 0x0908); // !!! = 0x51ffffff
write32 (DEFAULT_DMIBAR | 0x0908, 0x51ffffff);
read32 (DEFAULT_DMIBAR | 0x0928); // !!! = 0x51ffffff
write32 (DEFAULT_DMIBAR | 0x0928, 0x51ffffff);
read32 (DEFAULT_DMIBAR | 0x0c00); // !!! = 0x29700c08
write32 (DEFAULT_DMIBAR | 0x0c00, 0x29700c08);
read32 (DEFAULT_DMIBAR | 0x0c0c); // !!! = 0x16063400
write32 (DEFAULT_DMIBAR | 0x0c0c, 0x00063400);
read32 (DEFAULT_DMIBAR | 0x0700); // !!! = 0x46139008
write32 (DEFAULT_DMIBAR | 0x0700, 0x46339008);
read32 (DEFAULT_DMIBAR | 0x0720); // !!! = 0x46139008
write32 (DEFAULT_DMIBAR | 0x0720, 0x46339008);
read32 (DEFAULT_DMIBAR | 0x0700); // !!! = 0x46339008
write32 (DEFAULT_DMIBAR | 0x0700, 0x45339008);
read32 (DEFAULT_DMIBAR | 0x0720); // !!! = 0x46339008
write32 (DEFAULT_DMIBAR | 0x0720, 0x45339008);
read32 (DEFAULT_DMIBAR | 0x0700); // !!! = 0x45339008
write32 (DEFAULT_DMIBAR | 0x0700, 0x453b9008);
read32 (DEFAULT_DMIBAR | 0x0720); // !!! = 0x45339008
write32 (DEFAULT_DMIBAR | 0x0720, 0x453b9008);
read32 (DEFAULT_DMIBAR | 0x0700); // !!! = 0x453b9008
write32 (DEFAULT_DMIBAR | 0x0700, 0x45bb9008);
read32 (DEFAULT_DMIBAR | 0x0720); // !!! = 0x453b9008
write32 (DEFAULT_DMIBAR | 0x0720, 0x45bb9008);
read32 (DEFAULT_DMIBAR | 0x0700); // !!! = 0x45bb9008
write32 (DEFAULT_DMIBAR | 0x0700, 0x45fb9008);
read32 (DEFAULT_DMIBAR | 0x0720); // !!! = 0x45bb9008
write32 (DEFAULT_DMIBAR | 0x0720, 0x45fb9008);
read32 (DEFAULT_DMIBAR | 0x0914); // !!! = 0x9021a080
write32 (DEFAULT_DMIBAR | 0x0914, 0x9021a280);
read32 (DEFAULT_DMIBAR | 0x0934); // !!! = 0x9021a080
write32 (DEFAULT_DMIBAR | 0x0934, 0x9021a280);
read32 (DEFAULT_DMIBAR | 0x0914); // !!! = 0x9021a280
write32 (DEFAULT_DMIBAR | 0x0914, 0x9821a280);
read32 (DEFAULT_DMIBAR | 0x0934); // !!! = 0x9021a280
write32 (DEFAULT_DMIBAR | 0x0934, 0x9821a280);
read32 (DEFAULT_DMIBAR | 0x0a00); // !!! = 0x03042018
write32 (DEFAULT_DMIBAR | 0x0a00, 0x03242018);
read32 (DEFAULT_DMIBAR | 0x0a10); // !!! = 0x03042018
write32 (DEFAULT_DMIBAR | 0x0a10, 0x03242018);
read32 (DEFAULT_DMIBAR | 0x0a20); // !!! = 0x03042018
write32 (DEFAULT_DMIBAR | 0x0a20, 0x03242018);
read32 (DEFAULT_DMIBAR | 0x0a30); // !!! = 0x03042018
write32 (DEFAULT_DMIBAR | 0x0a30, 0x03242018);
read32 (DEFAULT_DMIBAR | 0x0258); // !!! = 0x40000600
write32 (DEFAULT_DMIBAR | 0x0258, 0x60000600);
read32 (DEFAULT_DMIBAR | 0x0904); // !!! = 0x3a1846ec
write32 (DEFAULT_DMIBAR | 0x0904, 0x2a1846ec);
read32 (DEFAULT_DMIBAR | 0x0914); // !!! = 0x9821a280
write32 (DEFAULT_DMIBAR | 0x0914, 0x98200280);
read32 (DEFAULT_DMIBAR | 0x0924); // !!! = 0x3a1846ec
write32 (DEFAULT_DMIBAR | 0x0924, 0x2a1846ec);
read32 (DEFAULT_DMIBAR | 0x0934); // !!! = 0x9821a280
write32 (DEFAULT_DMIBAR | 0x0934, 0x98200280);
read32 (DEFAULT_DMIBAR | 0x022c); // !!! = 0x00c26460
write32 (DEFAULT_DMIBAR | 0x022c, 0x00c2403c);
read8 (DEFAULT_RCBA | 0x21a4); // !!! = 0x42
read32 (DEFAULT_RCBA | 0x21a4); // !!! = 0x00012c42
read32 (DEFAULT_RCBA | 0x2340); // !!! = 0x0013001b
write32 (DEFAULT_RCBA | 0x2340, 0x003a001b);
read8 (DEFAULT_RCBA | 0x21b0); // !!! = 0x01
write8 (DEFAULT_RCBA | 0x21b0, 0x02);
read32 (DEFAULT_DMIBAR | 0x0084); // !!! = 0x0041ac41
write32 (DEFAULT_DMIBAR | 0x0084, 0x0041ac42);
read8 (DEFAULT_DMIBAR | 0x0088); // !!! = 0x00
write8 (DEFAULT_DMIBAR | 0x0088, 0x20);
read16 (DEFAULT_DMIBAR | 0x008a); // !!! = 0x0041
read8 (DEFAULT_DMIBAR | 0x0088); // !!! = 0x00
write8 (DEFAULT_DMIBAR | 0x0088, 0x20);
read16 (DEFAULT_DMIBAR | 0x008a); // !!! = 0x0042
read16 (DEFAULT_DMIBAR | 0x008a); // !!! = 0x0042
read32 (DEFAULT_DMIBAR | 0x0014); // !!! = 0x8000007f
write32 (DEFAULT_DMIBAR | 0x0014, 0x80000019);
read32 (DEFAULT_DMIBAR | 0x0020); // !!! = 0x01000000
write32 (DEFAULT_DMIBAR | 0x0020, 0x81000022);
read32 (DEFAULT_DMIBAR | 0x002c); // !!! = 0x02000000
write32 (DEFAULT_DMIBAR | 0x002c, 0x82000044);
read32 (DEFAULT_DMIBAR | 0x0038); // !!! = 0x07000080
write32 (DEFAULT_DMIBAR | 0x0038, 0x87000080);
read8 (DEFAULT_DMIBAR | 0x0004); // !!! = 0x00
write8 (DEFAULT_DMIBAR | 0x0004, 0x01);
read32 (DEFAULT_RCBA | 0x0050); // !!! = 0x01200654
write32 (DEFAULT_RCBA | 0x0050, 0x01200654);
read32 (DEFAULT_RCBA | 0x0050); // !!! = 0x01200654
write32 (DEFAULT_RCBA | 0x0050, 0x012a0654);
read32 (DEFAULT_RCBA | 0x0050); // !!! = 0x012a0654
read8 (DEFAULT_RCBA | 0x1114); // !!! = 0x00
write8 (DEFAULT_RCBA | 0x1114, 0x05);
read32 (DEFAULT_RCBA | 0x2014); // !!! = 0x80000011
write32 (DEFAULT_RCBA | 0x2014, 0x80000019);
read32 (DEFAULT_RCBA | 0x2020); // !!! = 0x00000000
write32 (DEFAULT_RCBA | 0x2020, 0x81000022);
read32 (DEFAULT_RCBA | 0x2020); // !!! = 0x81000022
read32 (DEFAULT_RCBA | 0x2030); // !!! = 0x00000000
write32 (DEFAULT_RCBA | 0x2030, 0x82000044);
read32 (DEFAULT_RCBA | 0x2030); // !!! = 0x82000044
read32 (DEFAULT_RCBA | 0x2040); // !!! = 0x00000000
write32 (DEFAULT_RCBA | 0x2040, 0x87000080);
read32 (DEFAULT_RCBA | 0x0050); // !!! = 0x012a0654
write32 (DEFAULT_RCBA | 0x0050, 0x812a0654);
read32 (DEFAULT_RCBA | 0x0050); // !!! = 0x812a0654
read16 (DEFAULT_RCBA | 0x201a); // !!! = 0x0000
read16 (DEFAULT_RCBA | 0x2026); // !!! = 0x0000
read16 (DEFAULT_RCBA | 0x2036); // !!! = 0x0000
read16 (DEFAULT_RCBA | 0x2046); // !!! = 0x0000
read16 (DEFAULT_DMIBAR | 0x001a); // !!! = 0x0000
read16 (DEFAULT_DMIBAR | 0x0026); // !!! = 0x0000
read16 (DEFAULT_DMIBAR | 0x0032); // !!! = 0x0000
read16 (DEFAULT_DMIBAR | 0x003e); // !!! = 0x0000
}
void
early_pch_init_native (void)
{
pcie_write_config8 (SOUTHBRIDGE, 0xa6,
pcie_read_config8 (SOUTHBRIDGE, 0xa6) | 2);
write32 (DEFAULT_RCBA | 0x2088, 0x00109000);
read32 (DEFAULT_RCBA | 0x20ac); // !!! = 0x00000000
write32 (DEFAULT_RCBA | 0x20ac, 0x40000000);
write32 (DEFAULT_RCBA | 0x100c, 0x01110000);
write8 (DEFAULT_RCBA | 0x2340, 0x1b);
read32 (DEFAULT_RCBA | 0x2314); // !!! = 0x0a080000
write32 (DEFAULT_RCBA | 0x2314, 0x0a280000);
read32 (DEFAULT_RCBA | 0x2310); // !!! = 0xc809605b
write32 (DEFAULT_RCBA | 0x2310, 0xa809605b);
write32 (DEFAULT_RCBA | 0x2324, 0x00854c74);
read8 (DEFAULT_RCBA | 0x0400); // !!! = 0x00
read32 (DEFAULT_RCBA | 0x2310); // !!! = 0xa809605b
write32 (DEFAULT_RCBA | 0x2310, 0xa809605b);
read32 (DEFAULT_RCBA | 0x2310); // !!! = 0xa809605b
write32 (DEFAULT_RCBA | 0x2310, 0xa809605b);
write_2338 (0xea007f62, 0x00590133);
write_2338 (0xec007f62, 0x00590133);
write_2338 (0xec007f64, 0x59555588);
write_2338 (0xea0040b9, 0x0001051c);
write_2338 (0xeb0040a1, 0x800084ff);
write_2338 (0xec0040a1, 0x800084ff);
write_2338 (0xea004001, 0x00008400);
write_2338 (0xeb004002, 0x40201758);
write_2338 (0xec004002, 0x40201758);
write_2338 (0xea004002, 0x00601758);
write_2338 (0xea0040a1, 0x810084ff);
write_2338 (0xeb0040b1, 0x0001c598);
write_2338 (0xec0040b1, 0x0001c598);
write_2338 (0xeb0040b6, 0x0001c598);
write_2338 (0xea0000a9, 0x80ff969f);
write_2338 (0xea0001a9, 0x80ff969f);
write_2338 (0xeb0040b2, 0x0001c396);
write_2338 (0xeb0040b3, 0x0001c396);
write_2338 (0xec0040b2, 0x0001c396);
write_2338 (0xea0001a9, 0x80ff94ff);
write_2338 (0xea000151, 0x0088037f);
write_2338 (0xea0000a9, 0x80ff94ff);
write_2338 (0xea000051, 0x0088037f);
write_2338 (0xea007f05, 0x00010642);
write_2338 (0xea0040b7, 0x0001c91c);
write_2338 (0xea0040b8, 0x0001c91c);
write_2338 (0xeb0040a1, 0x820084ff);
write_2338 (0xec0040a1, 0x820084ff);
write_2338 (0xea007f0a, 0xc2480000);
write_2338 (0xec00404d, 0x1ff177f);
write_2338 (0xec000084, 0x5a600000);
write_2338 (0xec000184, 0x5a600000);
write_2338 (0xec000284, 0x5a600000);
write_2338 (0xec000384, 0x5a600000);
write_2338 (0xec000094, 0x000f0501);
write_2338 (0xec000194, 0x000f0501);
write_2338 (0xec000294, 0x000f0501);
write_2338 (0xec000394, 0x000f0501);
write_2338 (0xec000096, 0x00000001);
write_2338 (0xec000196, 0x00000001);
write_2338 (0xec000296, 0x00000001);
write_2338 (0xec000396, 0x00000001);
write_2338 (0xec000001, 0x00008c08);
write_2338 (0xec000101, 0x00008c08);
write_2338 (0xec000201, 0x00008c08);
write_2338 (0xec000301, 0x00008c08);
write_2338 (0xec0040b5, 0x0001c518);
write_2338 (0xec000087, 0x06077597);
write_2338 (0xec000187, 0x06077597);
write_2338 (0xec000287, 0x06077597);
write_2338 (0xec000387, 0x06077597);
write_2338 (0xea000050, 0x00bb0157);
write_2338 (0xea000150, 0x00bb0157);
write_2338 (0xec007f60, 0x77777d77);
write_2338 (0xea00008d, 0x01320000);
write_2338 (0xea00018d, 0x01320000);
write_2338 (0xec0007b2, 0x04514b5e);
write_2338 (0xec00078c, 0x40000200);
write_2338 (0xec000780, 0x02000020);
init_dmi();
}

70
src/southbridge/intel/bd82x6x/early_thermal.c Normal file
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@ -0,0 +1,70 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Vladimir Serbinenko
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/io.h>
#include "pch.h"
#include "cpu/intel/model_206ax/model_206ax.h"
#include <cpu/x86/msr.h>
/* Early thermal init, must be done prior to giving ME its memory
which is done at the end of raminit. */
void early_thermal_init(void)
{
device_t dev;
msr_t msr;
dev = PCI_DEV(0x0, 0x1f, 0x6);
/* Program address for temporary BAR. */
pci_write_config32(dev, 0x40, 0x40000000);
pci_write_config32(dev, 0x44, 0x0);
/* Activate temporary BAR. */
pci_write_config32(dev, 0x40,
pci_read_config32(dev, 0x40) | 5);
write16 (0x40000004, 0x3a2b);
write8 (0x4000000c, 0xff);
write8 (0x4000000d, 0x00);
write8 (0x4000000e, 0x40);
write8 (0x40000082, 0x00);
write8 (0x40000001, 0xba);
/* Perform init. */
/* Configure TJmax. */
msr = rdmsr(MSR_TEMPERATURE_TARGET);
write16(0x40000012, ((msr.lo >> 16) & 0xff) << 6);
/* Northbridge temperature slope and offset. */
write16(0x40000016, 0x808c);
write16 (0x40000014, 0xde87);
/* Enable thermal data reporting, processor, PCH and northbridge. */
write16(0x4000001a, (read16(0x4000001a) & ~0xf) | 0x10f0);
/* Disable temporary BAR. */
pci_write_config32(dev, 0x40,
pci_read_config32(dev, 0x40) & ~1);
pci_write_config32(dev, 0x40, 0);
write32 (DEFAULT_RCBA | 0x38b0,
(read32 (DEFAULT_RCBA | 0x38b0) & 0xffff8003) | 0x403c);
}

2
src/southbridge/intel/bd82x6x/pch.h
View File

@ -74,6 +74,8 @@ void enable_smbus(void);
void enable_usb_bar(void);
int smbus_read_byte(unsigned device, unsigned address);
int early_spi_read(u32 offset, u32 size, u8 *buffer);
void early_thermal_init(void);
void early_pch_init_native(void);
#endif
#endif

3
src/southbridge/intel/bd82x6x/smi.c
View File

@ -29,10 +29,7 @@
#include <cpu/x86/smm.h>
#include <string.h>
#include "pch.h"
#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE
#include "northbridge/intel/sandybridge/sandybridge.h"
#endif
extern unsigned char _binary_smm_start;
extern unsigned char _binary_smm_end;

33
src/southbridge/intel/bd82x6x/usb_ehci.c
View File

@ -18,6 +18,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <kconfig.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
@ -36,11 +37,43 @@ static void usb_ehci_init(struct device *dev)
RCBA32(0x35b0) = reg32;
printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");
/* For others, done in MRC. */
#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE)
pci_write_config32(dev, 0x84, 0x930c8811);
pci_write_config32(dev, 0x88, 0x24000d30);
pci_write_config32(dev, 0xf4, 0x80408588);
pci_write_config32(dev, 0xf4, 0x80808588);
pci_write_config32(dev, 0xf4, 0x00808588);
pci_write_config32(dev, 0xfc, 0x205b1708);
#endif
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_MASTER;
//reg32 |= PCI_COMMAND_SERR;
pci_write_config32(dev, PCI_COMMAND, reg32);
/* For others, done in MRC. */
#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE)
struct resource *res;
u8 access_cntl;
access_cntl = pci_read_config8(dev, 0x80);
/* Enable writes to protected registers. */
pci_write_config8(dev, 0x80, access_cntl | 1);
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
/* Number of ports and companion controllers. */
reg32 = read32(res->base + 4);
write32(res->base + 4, (reg32 & 0xfff00000) | 3);
}
/* Restore protection. */
pci_write_config8(dev, 0x80, access_cntl);
#endif
printk(BIOS_DEBUG, "done.\n");
}