Change Geode GX2 to use the auto DRAM detect code from Geode LX.
Also, change the GX2 boards to use it. Add a processor speed setting function in human readable MHz and remove the useless and broken PLLMSR settings (the processor speed was hardcoded to 366MHz in pll_reset.c). Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6011 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Nils Jacobs
Uwe Hermann
parent
9644623934
commit
76890dde14
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@ -413,6 +413,13 @@
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#define AES_GLD_MSR_PM (MSR_AES + 0x2004)
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#define AES_CONTROL (MSR_AES + 0x2006)
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/* from MC spec */
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#define MIN_MOD_BANKS 1
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#define MAX_MOD_BANKS 2
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#define MIN_DEV_BANKS 2
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#define MAX_DEV_BANKS 4
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#define MAX_COL_ADDR 17
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/* more fun stuff */
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#define BM 1 /* Base Mask - map power of 2 size aligned region */
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#define BMO 2 /* BM with an offset */
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@ -15,87 +15,21 @@
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#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
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#include "southbridge/amd/cs5536/cs5536_early_setup.c"
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#define DIMM0 0xA0
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#define DIMM1 0xA2
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static inline int spd_read_byte(unsigned device, unsigned address)
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{
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return smbus_read_byte(device, address);
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if (device != DIMM0)
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return 0xFF; /* No DIMM1, don't even try. */
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return smbus_read_byte(device, address);
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}
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#include "northbridge/amd/gx2/raminit.h"
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static inline unsigned int fls(unsigned int x)
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{
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int r;
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__asm__("bsfl %1,%0\n\t"
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"jnz 1f\n\t"
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"movl $32,%0\n"
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"1:" : "=r" (r) : "g" (x));
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return r;
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}
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static void sdram_set_spd_registers(const struct mem_controller *ctrl)
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{
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/* Total size of DIMM = 2^row address (byte 3) * 2^col address (byte 4) *
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* component Banks (byte 17) * module banks, side (byte 5) *
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* width in bits (byte 6,7)
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* = Density per side (byte 31) * number of sides (byte 5) */
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/* 1. Initialize GLMC registers base on SPD values, do one DIMM for now */
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msr_t msr;
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unsigned char module_banks, val;
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msr = rdmsr(MC_CF07_DATA);
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/* get module banks (sides) per dimm, SPD byte 5 */
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module_banks = spd_read_byte(0xA0, 5);
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if (module_banks < 1 || module_banks > 2)
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print_err("Module banks per dimm\n");
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module_banks >>= 1;
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msr.hi &= ~(1 << CF07_UPPER_D0_MB_SHIFT);
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msr.hi |= (module_banks << CF07_UPPER_D0_MB_SHIFT);
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/* get component banks per module bank, SPD byte 17 */
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val = spd_read_byte(0xA0, 17);
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if (val < 2 || val > 4)
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print_err("Component banks per module bank\n");
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val >>= 2;
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msr.hi &= ~(0x1 << CF07_UPPER_D0_CB_SHIFT);
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msr.hi |= (val << CF07_UPPER_D0_CB_SHIFT);
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/* get the module bank density, SPD byte 31 */
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val = spd_read_byte(0xA0, 31);
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val = fls(val);
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val <<= module_banks;
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msr.hi &= ~(0xf << CF07_UPPER_D0_SZ_SHIFT);
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msr.hi |= (val << CF07_UPPER_D0_SZ_SHIFT);
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/* page size = 2^col address */
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val = spd_read_byte(0xA0, 4);
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val -= 7;
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msr.hi &= ~(0x7 << CF07_UPPER_D0_PSZ_SHIFT);
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msr.hi |= (val << CF07_UPPER_D0_PSZ_SHIFT);
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print_debug("computed msr.hi ");
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print_debug_hex32(msr.hi);
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print_debug("\n");
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msr.lo = 0x00003000;
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wrmsr(MC_CF07_DATA, msr);
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msr = rdmsr(0x20000019);
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msr.hi = 0x18000108;
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msr.lo = 0x696332a3;
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wrmsr(0x20000019, msr);
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}
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#include "northbridge/amd/gx2/pll_reset.c"
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#include "northbridge/amd/gx2/raminit.c"
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#include "lib/generic_sdram.c"
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#define PLLMSRhi 0x00001490
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#define PLLMSRlo 0x02000030
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#define PLLMSRlo1 ((0xde << 16) | (1 << 26) | (1 << 24))
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#define PLLMSRlo2 ((1<<14) |(1<<13) | (1<<0))
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#include "northbridge/amd/gx2/pll_reset.c"
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#include "cpu/amd/model_gx2/cpureginit.c"
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#include "cpu/amd/model_gx2/syspreinit.c"
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#include "cpu/amd/model_lx/msrinit.c"
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@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select CPU_AMD_GX2
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select NORTHBRIDGE_AMD_GX2
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select SOUTHBRIDGE_AMD_CS5535
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select HAVE_DEBUG_SMBUS
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select UDELAY_TSC
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select HAVE_PIRQ_TABLE
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select BOARD_ROMSIZE_KB_256
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@ -1,4 +1,5 @@
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#include <stdint.h>
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#include <spd.h>
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#include <device/pci_def.h>
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#include <arch/io.h>
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#include <device/pnp_def.h>
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@ -15,35 +16,61 @@
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#include "southbridge/amd/cs5535/cs5535_early_smbus.c"
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#include "southbridge/amd/cs5535/cs5535_early_setup.c"
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#include "northbridge/amd/gx2/raminit.h"
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/* this has to be done on a per-mainboard basis, esp. if you don't have smbus */
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static void sdram_set_spd_registers(const struct mem_controller *ctrl)
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#define DIMM0 0xA0
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#define DIMM1 0xA2
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static const unsigned char spdbytes[] = { /* 4x Qimonda HYB25DC512160CF-6 */
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0xFF, 0xFF, /* only values used by raminit.c are set */
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[SPD_MEMORY_TYPE] = SPD_MEMORY_TYPE_SDRAM_DDR, /* (Fundamental) memory type */
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[SPD_NUM_ROWS] = 0x0D, /* Number of row address bits [13] */
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[SPD_NUM_COLUMNS] = 0x0A, /* Number of column address bits [10] */
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[SPD_NUM_DIMM_BANKS] = 1, /* Number of module rows (banks) */
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0xFF, 0xFF, 0xFF,
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[SPD_MIN_CYCLE_TIME_AT_CAS_MAX] = 0x60, /* SDRAM cycle time (highest CAS latency), RAS access time (tRAC) [6.0 ns in BCD] */
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0xFF, 0xFF,
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[SPD_REFRESH] = 0x82, /* Refresh rate/type [Self Refresh, 7.8 us] */
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[SPD_PRIMARY_SDRAM_WIDTH] = 64, /* SDRAM width (primary SDRAM) [64 bits] */
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0xFF, 0xFF, 0xFF,
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[SPD_NUM_BANKS_PER_SDRAM] = 4, /* SDRAM device attributes, number of banks on SDRAM device */
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[SPD_ACCEPTABLE_CAS_LATENCIES] = 0x1C, /* SDRAM device attributes, CAS latency [3, 2.5, 2] */
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0xFF, 0xFF,
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[SPD_MODULE_ATTRIBUTES] = 0x20, /* SDRAM module attributes [differential clk] */
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[SPD_DEVICE_ATTRIBUTES_GENERAL] = 0x40, /* SDRAM device attributes, general [Concurrent AP] */
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[SPD_SDRAM_CYCLE_TIME_2ND] = 0x60, /* SDRAM cycle time (2nd highest CAS latency) [6.0 ns in BCD] */
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0xFF,
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[SPD_SDRAM_CYCLE_TIME_3RD] = 0x75, /* SDRAM cycle time (3rd highest CAS latency) [7.5 ns in BCD] */
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0xFF,
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[SPD_tRP] = 72, /* Min. row precharge time [18 ns in units of 0.25 ns] */
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[SPD_tRRD] = 48, /* Min. row active to row active [12 ns in units of 0.25 ns] */
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[SPD_tRCD] = 72, /* Min. RAS to CAS delay [18 ns in units of 0.25 ns] */
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[SPD_tRAS] = 42, /* Min. RAS pulse width = active to precharge delay [42 ns] */
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[SPD_BANK_DENSITY] = 0x40, /* Density of each row on module [256 MB] */
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0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
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[SPD_tRFC] = 72 /* SDRAM Device Minimum Auto Refresh to Active/Auto Refresh [72 ns] */
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};
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static inline int spd_read_byte(unsigned int device, unsigned int address)
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{
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msr_t msr;
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/* 1. Initialize GLMC registers base on SPD values,
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* Hard coded as XpressROM for now */
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//print_debug("sdram_enable step 1\n");
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msr = rdmsr(0x20000018);
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msr.hi = 0x10076013;
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msr.lo = 0x3400;
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wrmsr(0x20000018, msr);
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if (device != DIMM0)
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return 0xFF; /* No DIMM1, don't even try. */
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msr = rdmsr(0x20000019);
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msr.hi = 0x18000008;
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msr.lo = 0x696332a3;
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wrmsr(0x20000019, msr);
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#if CONFIG_DEBUG_SMBUS
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if (address >= sizeof(spdbytes) || spdbytes[address] == 0xFF) {
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print_err("ERROR: spd_read_byte(DIMM0, 0x");
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print_err_hex8(address);
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print_err(") returns 0xff\n");
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}
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#endif
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/* Fake SPD ROM value */
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return (address < sizeof(spdbytes)) ? spdbytes[address] : 0xFF;
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}
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#include "northbridge/amd/gx2/raminit.h"
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#include "northbridge/amd/gx2/pll_reset.c"
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#include "northbridge/amd/gx2/raminit.c"
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#include "lib/generic_sdram.c"
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#define PLLMSRhi 0x00000226
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#define PLLMSRlo 0x00000008
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#define PLLMSRlo1 ((0xde << 16) | (1 << 26) | (1 << 24))
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#define PLLMSRlo2 ((1<<14) |(1<<13) | (1<<0))
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#include "northbridge/amd/gx2/pll_reset.c"
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#include "cpu/amd/model_gx2/cpureginit.c"
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#include "cpu/amd/model_gx2/syspreinit.c"
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#include "cpu/amd/model_lx/msrinit.c"
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@ -34,92 +34,21 @@
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#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
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#include "southbridge/amd/cs5536/cs5536_early_setup.c"
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static inline int spd_read_byte(unsigned device, unsigned address)
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#define DIMM0 0xA0
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#define DIMM1 0xA2
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static inline int spd_read_byte(unsigned int device, unsigned int address)
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{
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return smbus_read_byte(device, address);
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if (device != DIMM0)
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return 0xFF; /* No DIMM1, don't even try. */
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return smbus_read_byte(device, address);
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}
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#include "northbridge/amd/gx2/raminit.h"
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/* This is needed because ROMCC doesn`t now the ctz bitop */
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static inline unsigned int ctz(unsigned int n)
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{
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int zeros;
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n = (n ^ (n - 1)) >> 1;
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for (zeros = 0; n; zeros++)
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{
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n >>= 1;
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}
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return zeros;
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}
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static void sdram_set_spd_registers(const struct mem_controller *ctrl)
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{
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/* Total size of DIMM = 2^row address (byte 3) * 2^col address (byte 4) *
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* component Banks (byte 17) * module banks, side (byte 5) *
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* width in bits (byte 6,7)
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* = Density per side (byte 31) * number of sides (byte 5) */
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/* 1. Initialize GLMC registers base on SPD values, do one DIMM for now */
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msr_t msr;
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unsigned char module_banks, val;
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uint16_t dimm_size;
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msr = rdmsr(MC_CF07_DATA);
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/* get module banks (sides) per dimm, SPD byte 5 */
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module_banks = spd_read_byte(0xA0, 5);
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if (module_banks < 1 || module_banks > 2)
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print_err("Module banks per dimm\n");
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module_banks >>= 1;
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msr.hi &= ~(1 << CF07_UPPER_D0_MB_SHIFT);
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msr.hi |= (module_banks << CF07_UPPER_D0_MB_SHIFT);
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/* get component banks per module bank, SPD byte 17 */
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val = spd_read_byte(0xA0, 17);
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if (val < 2 || val > 4)
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print_err("Component banks per module bank\n");
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val >>= 2;
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msr.hi &= ~(0x1 << CF07_UPPER_D0_CB_SHIFT);
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msr.hi |= (val << CF07_UPPER_D0_CB_SHIFT);
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dimm_size = spd_read_byte(0xA0, 31);
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dimm_size |= (dimm_size << 8); /* align so 1GB(bit0) is bit 8, this is a little weird to get gcc to not optimize this out */
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dimm_size &= 0x01FC; /* and off 2GB DIMM size : not supported and the 1GB size we just moved up to bit 8 as well as all the extra on top */
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/* Module Density * Module Banks */
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dimm_size <<= (0 >> CF07_UPPER_D0_MB_SHIFT) & 1; /* shift to multiply by # DIMM banks */
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if (dimm_size != 0) {
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dimm_size = ctz(dimm_size);
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}
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if (dimm_size > 7) { /* 7 is 512MB only support 512MB per DIMM */
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print_err("Only support up to 512MB \n");
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hlt();
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}
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msr.hi |= dimm_size << CF07_UPPER_D0_SZ_SHIFT;
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/* page size = 2^col address */
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val = spd_read_byte(0xA0, 4);
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val -= 7;
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msr.hi &= ~(0x7 << CF07_UPPER_D0_PSZ_SHIFT);
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msr.hi |= (val << CF07_UPPER_D0_PSZ_SHIFT);
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print_debug("computed msr.hi ");
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print_debug_hex32(msr.hi);
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print_debug("\n");
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msr.lo = 0x00003400;
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wrmsr(MC_CF07_DATA, msr);
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msr = rdmsr(MC_CF8F_DATA);
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msr.hi = 0x18000008;
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msr.lo = 0x296332a3;
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wrmsr(MC_CF8F_DATA, msr);
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}
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#include "northbridge/amd/gx2/pll_reset.c"
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#include "northbridge/amd/gx2/raminit.c"
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#include "lib/generic_sdram.c"
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#include "northbridge/amd/gx2/pll_reset.c"
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#include "cpu/amd/model_gx2/cpureginit.c"
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#include "cpu/amd/model_gx2/syspreinit.c"
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#include "cpu/amd/model_lx/msrinit.c"
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@ -21,3 +21,9 @@ config NORTHBRIDGE_AMD_GX2
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bool
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select GEODE_VSA
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# Valid PROCESSOR_MHZ options: 300/366/400 MHz.
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config PROCESSOR_MHZ
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int
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default 366
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depends on NORTHBRIDGE_AMD_GX2
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@ -63,13 +63,25 @@ static const unsigned char fbdiv2plldiv[] = {
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#define DEFAULT_MDIV 3
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#define DEFAULT_VDIV 2
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#define DEFAULT_FBDIV 22 // 366/244 ; 24 400/266 018 ;300/200
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static void pll_reset(void)
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{
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msr_t msrGlcpSysRstpll;
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unsigned MDIV_VDIV_FBDIV;
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unsigned SyncBits; /* store the sync bits in up ebx */
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unsigned DEFAULT_FBDIV;
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if (CONFIG_PROCESSOR_MHZ == 400) {
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DEFAULT_FBDIV = 24;
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} else if (CONFIG_PROCESSOR_MHZ == 366) {
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DEFAULT_FBDIV = 22;
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} else if (CONFIG_PROCESSOR_MHZ == 300) {
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DEFAULT_FBDIV = 18;
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} else {
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printk(BIOS_ERR, "Unsupported PROCESSOR_MHZ setting!\n");
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post_code(POST_PLL_CPU_VER_FAIL);
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__asm__ __volatile__("hlt\n");
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}
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/* clear the Bypass bit */
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@ -179,3 +191,10 @@ static void pll_reset(void)
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} /* we haven't configured the PLL; do it now */
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}
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static unsigned int GeodeLinkSpeed(void)
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{
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unsigned geodelinkspeed;
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geodelinkspeed = ((CONFIG_PROCESSOR_MHZ * DEFAULT_VDIV) / DEFAULT_MDIV);
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return (geodelinkspeed);
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}
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@ -1,7 +1,521 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
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* Copyright (C) 2010 Nils Jacobs
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
|
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*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <cpu/amd/gx2def.h>
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#include <spd.h>
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static const unsigned char NumColAddr[] = {
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0x00, 0x10, 0x11, 0x00, 0x00, 0x00, 0x00, 0x07,
|
||||
0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
|
||||
};
|
||||
|
||||
static void banner(const char *s)
|
||||
{
|
||||
printk(BIOS_DEBUG, " * %s\n", s);
|
||||
}
|
||||
|
||||
static void hcf(void)
|
||||
{
|
||||
print_emerg("DIE\n");
|
||||
/* this guarantees we flush the UART fifos (if any) and also
|
||||
* ensures that things, in general, keep going so no debug output
|
||||
* is lost
|
||||
*/
|
||||
while (1)
|
||||
print_emerg_char(0);
|
||||
}
|
||||
|
||||
static void auto_size_dimm(unsigned int dimm)
|
||||
{
|
||||
uint32_t dimm_setting;
|
||||
uint16_t dimm_size;
|
||||
uint8_t spd_byte;
|
||||
msr_t msr;
|
||||
|
||||
dimm_setting = 0;
|
||||
|
||||
banner("Check present");
|
||||
/* Check that we have a dimm */
|
||||
if (spd_read_byte(dimm, SPD_MEMORY_TYPE) == 0xFF) {
|
||||
return;
|
||||
}
|
||||
|
||||
banner("MODBANKS");
|
||||
/* Field: Module Banks per DIMM */
|
||||
/* EEPROM byte usage: (5) Number of DIMM Banks */
|
||||
spd_byte = spd_read_byte(dimm, SPD_NUM_DIMM_BANKS);
|
||||
if ((MIN_MOD_BANKS > spd_byte) || (spd_byte > MAX_MOD_BANKS)) {
|
||||
print_emerg("Number of module banks not compatible\n");
|
||||
post_code(ERROR_BANK_SET);
|
||||
hcf();
|
||||
}
|
||||
dimm_setting |= (spd_byte >> 1) << CF07_UPPER_D0_MB_SHIFT;
|
||||
banner("FIELDBANKS");
|
||||
|
||||
/* Field: Banks per SDRAM device */
|
||||
/* EEPROM byte usage: (17) Number of Banks on SDRAM Device */
|
||||
spd_byte = spd_read_byte(dimm, SPD_NUM_BANKS_PER_SDRAM);
|
||||
if ((MIN_DEV_BANKS > spd_byte) || (spd_byte > MAX_DEV_BANKS)) {
|
||||
print_emerg("Number of device banks not compatible\n");
|
||||
post_code(ERROR_BANK_SET);
|
||||
hcf();
|
||||
}
|
||||
dimm_setting |= (spd_byte >> 2) << CF07_UPPER_D0_CB_SHIFT;
|
||||
banner("SPDNUMROWS");
|
||||
|
||||
/*; Field: DIMM size
|
||||
*; EEPROM byte usage: (3) Number of Row Addresses
|
||||
*; (4) Number of Column Addresses
|
||||
*; (5) Number of DIMM Banks
|
||||
*; (31) Module Bank Density
|
||||
*; Size = Module Density * Module Banks
|
||||
*/
|
||||
if ((spd_read_byte(dimm, SPD_NUM_ROWS) & 0xF0)
|
||||
|| (spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF0)) {
|
||||
print_emerg("Assymetirc DIMM not compatible\n");
|
||||
post_code(ERROR_UNSUPPORTED_DIMM);
|
||||
hcf();
|
||||
}
|
||||
banner("SPDBANKDENSITY");
|
||||
|
||||
dimm_size = spd_read_byte(dimm, SPD_BANK_DENSITY);
|
||||
banner("DIMMSIZE");
|
||||
dimm_size |= (dimm_size << 8); /* align so 1GB(bit0) is bit 8, this is a little weird to get gcc to not optimize this out */
|
||||
dimm_size &= 0x01FC; /* and off 2GB DIMM size : not supported and the 1GB size we just moved up to bit 8 as well as all the extra on top */
|
||||
|
||||
/* Module Density * Module Banks */
|
||||
dimm_size <<= (dimm_setting >> CF07_UPPER_D0_MB_SHIFT) & 1; /* shift to multiply by # DIMM banks */
|
||||
banner("BEFORT CTZ");
|
||||
dimm_size = __builtin_ctz(dimm_size);
|
||||
banner("TEST DIMM SIZE>7");
|
||||
if (dimm_size > 7) { /* 7 is 512MB only support 512MB per DIMM */
|
||||
print_emerg("Only support up to 512MB per DIMM\n");
|
||||
post_code(ERROR_DENSITY_DIMM);
|
||||
hcf();
|
||||
}
|
||||
dimm_setting |= dimm_size << CF07_UPPER_D0_SZ_SHIFT;
|
||||
banner("PAGESIZE");
|
||||
|
||||
/*; Field: PAGE size
|
||||
*; EEPROM byte usage: (4) Number of Column Addresses
|
||||
*; PageSize = 2^# Column Addresses * Data width in bytes (should be 8bytes for a normal DIMM)
|
||||
*
|
||||
*; But this really works by magic.
|
||||
*; If ma[11:0] is the memory address pins, and pa[13:0] is the physical column address
|
||||
*; that MC generates, here is how the MC assigns the pa onto the ma pins:
|
||||
*
|
||||
*;ma 11 10 09 08 07 06 05 04 03 02 01 00
|
||||
*;--------------------------------------------------------------------------------------------------------------------------------------
|
||||
*;pa 09 08 07 06 05 04 03 (7 col addr bits = 1K page size)
|
||||
*;pa 10 09 08 07 06 05 04 03 (8 col addr bits = 2K page size)
|
||||
*;pa 11 10 09 08 07 06 05 04 03 (9 col addr bits = 4K page size)
|
||||
*;pa 12 11 10 09 08 07 06 05 04 03 (10 col addr bits = 8K page size)
|
||||
*;pa 13 AP 12 11 10 09 08 07 06 05 04 03 (11 col addr bits = 16K page size)
|
||||
*; *AP=autoprecharge bit
|
||||
*
|
||||
*; Remember that pa[2:0] are zeroed out since it's a 64-bit data bus (8 bytes),
|
||||
*; so lower 3 address bits are dont_cares.So from the table above,
|
||||
*; it's easier to see what the old code is doing: if for example,#col_addr_bits=7(06h),
|
||||
*; it adds 3 to get 10, then does 2^10=1K. Get it?*/
|
||||
|
||||
spd_byte = NumColAddr[spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF];
|
||||
banner("MAXCOLADDR");
|
||||
if (spd_byte > MAX_COL_ADDR) {
|
||||
print_emerg("DIMM page size not compatible\n");
|
||||
post_code(ERROR_SET_PAGE);
|
||||
hcf();
|
||||
}
|
||||
banner(">11address test");
|
||||
spd_byte -= 7;
|
||||
if (spd_byte > 4) { /* if the value is above 4 it means >11 col address lines */
|
||||
spd_byte = 7; /* which means >16k so set to disabled */
|
||||
}
|
||||
dimm_setting |= spd_byte << CF07_UPPER_D0_PSZ_SHIFT; /* 0=1k,1=2k,2=4k,etc */
|
||||
|
||||
banner("RDMSR CF07");
|
||||
msr = rdmsr(MC_CF07_DATA);
|
||||
banner("WRMSR CF07");
|
||||
if (dimm == DIMM0) {
|
||||
msr.hi &= 0xFFFF0000;
|
||||
msr.hi |= dimm_setting;
|
||||
} else {
|
||||
msr.hi &= 0x0000FFFF;
|
||||
msr.hi |= dimm_setting << 16;
|
||||
}
|
||||
wrmsr(MC_CF07_DATA, msr);
|
||||
banner("ALL DONE");
|
||||
}
|
||||
|
||||
static void checkDDRMax(void)
|
||||
{
|
||||
uint8_t spd_byte0, spd_byte1;
|
||||
uint16_t speed;
|
||||
|
||||
/* PC133 identifier */
|
||||
spd_byte0 = spd_read_byte(DIMM0, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
|
||||
if (spd_byte0 == 0xFF) {
|
||||
spd_byte0 = 0;
|
||||
}
|
||||
spd_byte1 = spd_read_byte(DIMM1, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
|
||||
if (spd_byte1 == 0xFF) {
|
||||
spd_byte1 = 0;
|
||||
}
|
||||
|
||||
/* Use the slowest DIMM */
|
||||
if (spd_byte0 < spd_byte1) {
|
||||
spd_byte0 = spd_byte1;
|
||||
}
|
||||
|
||||
/* Turn SPD ns time into MHZ. Check what the asm does to this math. */
|
||||
speed = 20000 / (((spd_byte0 >> 4) * 10) + (spd_byte0 & 0x0F));
|
||||
|
||||
/* current speed > max speed? */
|
||||
if (GeodeLinkSpeed() > speed) {
|
||||
print_emerg("DIMM overclocked. Check GeodeLink Speed\n");
|
||||
post_code(POST_PLL_MEM_FAIL);
|
||||
hcf();
|
||||
}
|
||||
}
|
||||
|
||||
const uint16_t REF_RATE[] = { 15, 3, 7, 31, 62, 125 }; /* ns */
|
||||
|
||||
static void set_refresh_rate(void)
|
||||
{
|
||||
uint8_t spd_byte0, spd_byte1;
|
||||
uint16_t rate0, rate1;
|
||||
msr_t msr;
|
||||
|
||||
spd_byte0 = spd_read_byte(DIMM0, SPD_REFRESH);
|
||||
spd_byte0 &= 0xF;
|
||||
if (spd_byte0 > 5) {
|
||||
spd_byte0 = 5;
|
||||
}
|
||||
rate0 = REF_RATE[spd_byte0];
|
||||
|
||||
spd_byte1 = spd_read_byte(DIMM1, SPD_REFRESH);
|
||||
spd_byte1 &= 0xF;
|
||||
if (spd_byte1 > 5) {
|
||||
spd_byte1 = 5;
|
||||
}
|
||||
rate1 = REF_RATE[spd_byte1];
|
||||
|
||||
/* Use the faster rate (lowest number) */
|
||||
if (rate0 > rate1) {
|
||||
rate0 = rate1;
|
||||
}
|
||||
|
||||
msr = rdmsr(MC_CF07_DATA);
|
||||
msr.lo |= ((rate0 * (GeodeLinkSpeed() / 2)) / 16)
|
||||
<< CF07_LOWER_REF_INT_SHIFT;
|
||||
wrmsr(MC_CF07_DATA, msr);
|
||||
}
|
||||
|
||||
const uint8_t CASDDR[] = { 5, 5, 2, 6, 0 }; /* 1(1.5), 1.5, 2, 2.5, 0 */
|
||||
|
||||
static u8 getcasmap(u32 dimm, u16 glspeed)
|
||||
{
|
||||
u16 dimm_speed;
|
||||
u8 spd_byte, casmap, casmap_shift=0;
|
||||
|
||||
/************************** DIMM0 **********************************/
|
||||
casmap = spd_read_byte(dimm, SPD_ACCEPTABLE_CAS_LATENCIES);
|
||||
if (casmap != 0xFF) {
|
||||
/* IF -.5 timing is supported, check -.5 timing > GeodeLink */
|
||||
spd_byte = spd_read_byte(dimm, SPD_SDRAM_CYCLE_TIME_2ND);
|
||||
if (spd_byte != 0) {
|
||||
/* Turn SPD ns time into MHZ. Check what the asm does to this math. */
|
||||
dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F));
|
||||
if (dimm_speed >= glspeed) {
|
||||
casmap_shift = 1; /* -.5 is a shift of 1 */
|
||||
/* IF -1 timing is supported, check -1 timing > GeodeLink */
|
||||
spd_byte = spd_read_byte(dimm, SPD_SDRAM_CYCLE_TIME_3RD);
|
||||
if (spd_byte != 0) {
|
||||
/* Turn SPD ns time into MHZ. Check what the asm does to this math. */
|
||||
dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F));
|
||||
if (dimm_speed >= glspeed) {
|
||||
casmap_shift = 2; /* -1 is a shift of 2 */
|
||||
}
|
||||
} /* SPD_SDRAM_CYCLE_TIME_3RD (-1) !=0 */
|
||||
} else {
|
||||
casmap_shift = 0;
|
||||
}
|
||||
} /* SPD_SDRAM_CYCLE_TIME_2ND (-.5) !=0 */
|
||||
/* set the casmap based on the shift to limit possible CAS settings */
|
||||
spd_byte = 31 - __builtin_clz((uint32_t) casmap);
|
||||
/* just want bits in the lower byte since we have to cast to a 32 */
|
||||
casmap &= 0xFF << (spd_byte - casmap_shift);
|
||||
} else { /* No DIMM */
|
||||
casmap = 0;
|
||||
}
|
||||
return casmap;
|
||||
}
|
||||
|
||||
static void setCAS(void)
|
||||
{
|
||||
/*;*****************************************************************************
|
||||
;*
|
||||
;* setCAS
|
||||
;* EEPROM byte usage: (18) SDRAM device attributes - CAS latency
|
||||
;* EEPROM byte usage: (23) SDRAM Minimum Clock Cycle Time @ CLX -.5
|
||||
;* EEPROM byte usage: (25) SDRAM Minimum Clock Cycle Time @ CLX -1
|
||||
;*
|
||||
;* The CAS setting is based on the information provided in each DIMMs SPD.
|
||||
;* The speed at which a DIMM can run is described relative to the slowest
|
||||
;* CAS the DIMM supports. Each speed for the relative CAS settings is
|
||||
;* checked that it is within the GeodeLink speed. If it isn't within the GeodeLink
|
||||
;* speed, the CAS setting is removed from the list of good settings for
|
||||
;* the DIMM. This is done for both DIMMs and the lists are compared to
|
||||
;* find the lowest common CAS latency setting. If there are no CAS settings
|
||||
;* in common we out a ERROR_DIFF_DIMMS (78h) to port 80h and halt.
|
||||
;*
|
||||
;* Entry:
|
||||
;* Exit: Set fastest CAS Latency based on GeodeLink speed and SPD information.
|
||||
;* Destroys: We really use everything !
|
||||
;*****************************************************************************/
|
||||
uint16_t glspeed;
|
||||
uint8_t spd_byte, casmap0, casmap1;
|
||||
msr_t msr;
|
||||
|
||||
glspeed = GeodeLinkSpeed();
|
||||
|
||||
casmap0 = getcasmap(DIMM0, glspeed);
|
||||
casmap1 = getcasmap(DIMM1, glspeed);
|
||||
|
||||
/********************* CAS_LAT MAP COMPARE ***************************/
|
||||
if (casmap0 == 0) {
|
||||
spd_byte = CASDDR[__builtin_ctz(casmap1)];
|
||||
} else if (casmap1 == 0) {
|
||||
spd_byte = CASDDR[__builtin_ctz(casmap0)];
|
||||
} else if ((casmap0 &= casmap1)) {
|
||||
spd_byte = CASDDR[__builtin_ctz(casmap0)];
|
||||
} else {
|
||||
print_emerg("DIMM CAS Latencies not compatible\n");
|
||||
post_code(ERROR_DIFF_DIMMS);
|
||||
hcf();
|
||||
}
|
||||
|
||||
msr = rdmsr(MC_CF8F_DATA);
|
||||
msr.lo &= ~(7 << CF8F_LOWER_CAS_LAT_SHIFT);
|
||||
msr.lo |= spd_byte << CF8F_LOWER_CAS_LAT_SHIFT;
|
||||
wrmsr(MC_CF8F_DATA, msr);
|
||||
}
|
||||
|
||||
static void set_latencies(void)
|
||||
{
|
||||
uint32_t memspeed, dimm_setting;
|
||||
uint8_t spd_byte0, spd_byte1;
|
||||
msr_t msr;
|
||||
|
||||
memspeed = GeodeLinkSpeed() / 2;
|
||||
dimm_setting = 0;
|
||||
|
||||
/* MC_CF8F setup */
|
||||
/* tRAS */
|
||||
spd_byte0 = spd_read_byte(DIMM0, SPD_tRAS);
|
||||
if (spd_byte0 == 0xFF) {
|
||||
spd_byte0 = 0;
|
||||
}
|
||||
spd_byte1 = spd_read_byte(DIMM1, SPD_tRAS);
|
||||
if (spd_byte1 == 0xFF) {
|
||||
spd_byte1 = 0;
|
||||
}
|
||||
if (spd_byte0 < spd_byte1) {
|
||||
spd_byte0 = spd_byte1;
|
||||
}
|
||||
/* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
|
||||
spd_byte1 = (spd_byte0 * memspeed) / 1000;
|
||||
if (((spd_byte0 * memspeed) % 1000)) {
|
||||
++spd_byte1;
|
||||
}
|
||||
if (spd_byte1 > 6) {
|
||||
--spd_byte1;
|
||||
}
|
||||
dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2PRE_SHIFT;
|
||||
|
||||
/* tRP */
|
||||
spd_byte0 = spd_read_byte(DIMM0, SPD_tRP);
|
||||
if (spd_byte0 == 0xFF) {
|
||||
spd_byte0 = 0;
|
||||
}
|
||||
spd_byte1 = spd_read_byte(DIMM1, SPD_tRP);
|
||||
if (spd_byte1 == 0xFF) {
|
||||
spd_byte1 = 0;
|
||||
}
|
||||
if (spd_byte0 < spd_byte1) {
|
||||
spd_byte0 = spd_byte1;
|
||||
}
|
||||
/* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
|
||||
spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000;
|
||||
if ((((spd_byte0 >> 2) * memspeed) % 1000)) {
|
||||
++spd_byte1;
|
||||
}
|
||||
dimm_setting |= spd_byte1 << CF8F_LOWER_PRE2ACT_SHIFT;
|
||||
|
||||
/* tRCD */
|
||||
spd_byte0 = spd_read_byte(DIMM0, SPD_tRCD);
|
||||
if (spd_byte0 == 0xFF) {
|
||||
spd_byte0 = 0;
|
||||
}
|
||||
spd_byte1 = spd_read_byte(DIMM1, SPD_tRCD);
|
||||
if (spd_byte1 == 0xFF) {
|
||||
spd_byte1 = 0;
|
||||
}
|
||||
if (spd_byte0 < spd_byte1) {
|
||||
spd_byte0 = spd_byte1;
|
||||
}
|
||||
/* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
|
||||
spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000;
|
||||
if ((((spd_byte0 >> 2) * memspeed) % 1000)) {
|
||||
++spd_byte1;
|
||||
}
|
||||
dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2CMD_SHIFT;
|
||||
|
||||
/* tRRD */
|
||||
spd_byte0 = spd_read_byte(DIMM0, SPD_tRRD);
|
||||
if (spd_byte0 == 0xFF) {
|
||||
spd_byte0 = 0;
|
||||
}
|
||||
spd_byte1 = spd_read_byte(DIMM1, SPD_tRRD);
|
||||
if (spd_byte1 == 0xFF) {
|
||||
spd_byte1 = 0;
|
||||
}
|
||||
if (spd_byte0 < spd_byte1) {
|
||||
spd_byte0 = spd_byte1;
|
||||
}
|
||||
/* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
|
||||
spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000;
|
||||
if ((((spd_byte0 >> 2) * memspeed) % 1000)) {
|
||||
++spd_byte1;
|
||||
}
|
||||
dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2ACT_SHIFT;
|
||||
|
||||
/* tRC = tRP + tRAS */
|
||||
dimm_setting |= (((dimm_setting >> CF8F_LOWER_ACT2PRE_SHIFT) & 0x0F) +
|
||||
((dimm_setting >> CF8F_LOWER_PRE2ACT_SHIFT) & 0x07))
|
||||
<< CF8F_LOWER_REF2ACT_SHIFT;
|
||||
|
||||
msr = rdmsr(MC_CF8F_DATA);
|
||||
msr.lo &= 0xF00000FF;
|
||||
msr.lo |= dimm_setting;
|
||||
msr.hi |= CF8F_UPPER_REORDER_DIS_SET;
|
||||
wrmsr(MC_CF8F_DATA, msr);
|
||||
printk(BIOS_DEBUG, "MSR MC_CF8F_DATA (%08x) value is %08x:%08x\n",
|
||||
MC_CF8F_DATA, msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
static void set_extended_mode_registers(void)
|
||||
{
|
||||
uint8_t spd_byte0, spd_byte1;
|
||||
msr_t msr;
|
||||
spd_byte0 = spd_read_byte(DIMM0, SPD_DEVICE_ATTRIBUTES_GENERAL);
|
||||
if (spd_byte0 == 0xFF) {
|
||||
spd_byte0 = 0;
|
||||
}
|
||||
spd_byte1 = spd_read_byte(DIMM1, SPD_DEVICE_ATTRIBUTES_GENERAL);
|
||||
if (spd_byte1 == 0xFF) {
|
||||
spd_byte1 = 0;
|
||||
}
|
||||
spd_byte1 &= spd_byte0;
|
||||
|
||||
msr = rdmsr(MC_CF07_DATA);
|
||||
if (spd_byte1 & 1) { /* Drive Strength Control */
|
||||
msr.lo |= CF07_LOWER_EMR_DRV_SET;
|
||||
}
|
||||
if (spd_byte1 & 2) { /* FET Control */
|
||||
msr.lo |= CF07_LOWER_EMR_QFC_SET;
|
||||
}
|
||||
wrmsr(MC_CF07_DATA, msr);
|
||||
}
|
||||
|
||||
static void sdram_set_registers(const struct mem_controller *ctrl)
|
||||
{
|
||||
msr_t msr;
|
||||
uint32_t msrnum;
|
||||
|
||||
/* Set Refresh Staggering */
|
||||
msrnum = MC_CF07_DATA;
|
||||
msr = rdmsr(msrnum);
|
||||
msr.lo &= ~0xC0;
|
||||
msr.lo |= 0x0; /* set refresh to 4SDRAM clocks */
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
/* Memory Interleave: Set HOI here otherwise default is LOI */
|
||||
/* msrnum = MC_CF8F_DATA;
|
||||
msr = rdmsr(msrnum);
|
||||
msr.hi |= CF8F_UPPER_HOI_LOI_SET;
|
||||
wrmsr(msrnum, msr); */
|
||||
}
|
||||
|
||||
static void sdram_set_spd_registers(const struct mem_controller *ctrl)
|
||||
{
|
||||
uint8_t spd_byte;
|
||||
|
||||
banner("sdram_set_spd_register");
|
||||
post_code(POST_MEM_SETUP); // post_70h
|
||||
|
||||
spd_byte = spd_read_byte(DIMM0, SPD_MODULE_ATTRIBUTES);
|
||||
banner("Check DIMM 0");
|
||||
/* Check DIMM is not Register and not Buffered DIMMs. */
|
||||
if ((spd_byte != 0xFF) && (spd_byte & 3)) {
|
||||
print_emerg("DIMM0 NOT COMPATIBLE\n");
|
||||
post_code(ERROR_UNSUPPORTED_DIMM);
|
||||
hcf();
|
||||
}
|
||||
banner("Check DIMM 1");
|
||||
spd_byte = spd_read_byte(DIMM1, SPD_MODULE_ATTRIBUTES);
|
||||
if ((spd_byte != 0xFF) && (spd_byte & 3)) {
|
||||
print_emerg("DIMM1 NOT COMPATIBLE\n");
|
||||
post_code(ERROR_UNSUPPORTED_DIMM);
|
||||
hcf();
|
||||
}
|
||||
|
||||
post_code(POST_MEM_SETUP2); // post_72h
|
||||
banner("Check DDR MAX");
|
||||
|
||||
/* Check that the memory is not overclocked. */
|
||||
checkDDRMax();
|
||||
|
||||
/* Size the DIMMS */
|
||||
post_code(POST_MEM_SETUP3); // post_73h
|
||||
banner("AUTOSIZE DIMM 0");
|
||||
auto_size_dimm(DIMM0);
|
||||
post_code(POST_MEM_SETUP4); // post_74h
|
||||
banner("AUTOSIZE DIMM 1");
|
||||
auto_size_dimm(DIMM1);
|
||||
|
||||
/* Set CAS latency */
|
||||
banner("set cas latency");
|
||||
post_code(POST_MEM_SETUP5); // post_75h
|
||||
setCAS();
|
||||
|
||||
/* Set all the other latencies here (tRAS, tRP....) */
|
||||
banner("set all latency");
|
||||
set_latencies();
|
||||
|
||||
/* Set Extended Mode Registers */
|
||||
banner("set emrs");
|
||||
set_extended_mode_registers();
|
||||
|
||||
banner("set ref rate");
|
||||
/* Set Memory Refresh Rate */
|
||||
set_refresh_rate();
|
||||
}
|
||||
|
||||
/* Section 6.1.3, LX processor databooks, BIOS Initialization Sequence
|
||||
|
|
@ -40,18 +554,6 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
|
|||
}
|
||||
//print_debug("sdram_enable step 4\n");
|
||||
|
||||
/* 5. set refresh interval */
|
||||
msr = rdmsr(0x20000018);
|
||||
msr.lo &= ~(0xffff << 8);
|
||||
msr.lo |= (0x34 << 8);
|
||||
wrmsr(0x20000018, msr);
|
||||
/* set refresh staggering to 4 SDRAM clocks */
|
||||
msr = rdmsr(0x20000018);
|
||||
msr.lo &= ~(0x03 << 6);
|
||||
msr.lo |= (0x00 << 6);
|
||||
wrmsr(0x20000018, msr);
|
||||
//print_debug("sdram_enable step 5\n");
|
||||
|
||||
/* 6. enable DLL, load Extended Mode Register by set and clear PROG_DRAM */
|
||||
msr = rdmsr(MC_CF07_DATA);
|
||||
msr.lo |= ((0x01 << 28) | 0x01);
|
||||
|
|
|
|||
Loading…
Reference in New Issue