mb/google/kukui: Add new ddr architecture support for kukui

Two configuration files are added:
1. H9HCNNNFAMMLXR-NEE-8GB: new byte mode
2. MT53E1G32D2NP-046-4GB: new single rank mode

Also initialize the rank number field 'rank_num' for all configs.

BUG=b:165768895
BRANCH=kukui
TEST=DDR boot up correctly on Kukui

Signed-off-by: Shaoming Chen <shaoming.chen@mediatek.corp-partner.google.com>
Change-Id: I1786c1e251e8d6e110cbdce79feeb386db220404
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49108
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/kukui/sdram_params/Makefile.inc

@@ -10,6 +10,8 @@ sdram-params += sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB
 sdram-params += sdram-lpddr4x-MT53E1G32D4NQ-4GB
 sdram-params += sdram-lpddr4x-MT53E2G32D4NQ-046-8GB
 sdram-params += sdram-lpddr4x-SDADA4CR-128G-4GB
+sdram-params += sdram-lpddr4x-H9HCNNNFAMMLXR-NEE-8GB
+sdram-params += sdram-lpddr4x-MT53E1G32D2NP-046-4GB
 
 $(foreach params,$(sdram-params), \
 	$(eval cbfs-files-y += $(params)) \

src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c

@@ -5,6 +5,7 @@
 struct sdram_params params = {
 	.source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG,
 	.frequency = 1600,
+	.rank_num = 2,
 	.ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2,
 	.wr_level = {
 		[CHANNEL_A] = { {0x22, 0x1b}, {0x22, 0x19} },

src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB.c

@@ -6,6 +6,7 @@ struct sdram_params params = {
 	.source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG,
 	.ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2,
 	.frequency = 1600,
+	.rank_num = 2,
 	.wr_level = {
 		[CHANNEL_A] = { {0x22, 0x1b}, {0x22, 0x19} },
 		[CHANNEL_B] = { {0x24, 0x20}, {0x25, 0x20} }

src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNFAMMLXR-NEE-8GB.c

@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/dramc_param.h>
+
+struct sdram_params params = {
+	.source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG,
+	.ddr_geometry = DDR_TYPE_2CH_RK0_RK1_BYTE_8GB_4_4,
+	.frequency = 1600,
+	.rank_num = 2,
+	.wr_level = {
+		[CHANNEL_A] = { {0x1F, 0x19}, {0x20, 0x1A} },
+		[CHANNEL_B] = { {0x22, 0x1E}, {0x22, 0x1E} }
+	},
+	.cbt_cs_dly = {
+		[CHANNEL_A] = {0x5, 0x4},
+		[CHANNEL_B] = {0x8, 0x8}
+	},
+	.cbt_final_vref = {
+		[CHANNEL_A] = {0x56, 0x56},
+		[CHANNEL_B] = {0x56, 0x56}
+	},
+	.emi_cona_val = 0xF053F154,
+	.emi_conh_val = 0x44440003,
+	.emi_conf_val = 0x00421000,
+	.chn_emi_cona_val = {0x0444F051, 0x0444F051},
+	.cbt_mode_extern = CBT_BYTE_MODE1,
+	.delay_cell_unit = 868,
+};

src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c

@@ -4,6 +4,7 @@
 
 struct sdram_params params = {
 	.source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG,
+	.rank_num = 2,
 	.frequency = 1600,
 	.ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2,
 	.wr_level = {

src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCR-4GB.c

@@ -5,6 +5,7 @@
 struct sdram_params params = {
 	.source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG,
 	.frequency = 1600,
+	.rank_num = 2,
 	.ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2,
 	.wr_level = {
 		[CHANNEL_A] = { {0x22, 0x1C}, {0x23, 0x1D} },

src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c

@@ -5,6 +5,7 @@
 struct sdram_params params = {
 	.source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG,
 	.frequency = 1600,
+	.rank_num = 2,
 	.ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2,
 	.wr_level = {
 		[CHANNEL_A] = { {0x21, 0x21}, {0x20, 0x20} },

src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c

@@ -4,6 +4,7 @@
 
 struct sdram_params params = {
 	.source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG,
+	.rank_num = 2,
 	.frequency = 1600,
 	.ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2,
 	.wr_level = {

src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c

@@ -5,6 +5,7 @@
 struct sdram_params params = {
 	.source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG,
 	.frequency = 1600,
+	.rank_num = 2,
 	.ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2,
 	.wr_level = {
 		[CHANNEL_A] = { {0x21, 0x24}, {0x22, 0x24} },

src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c

@@ -5,6 +5,7 @@
 struct sdram_params params = {
 	.source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG,
 	.frequency = 1600,
+	.rank_num = 2,
 	.ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2,
 	.wr_level = {
 		[CHANNEL_A] = { {0x21, 0x21}, {0x20, 0x20} },

src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D2NP-046-4GB.c

@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/dramc_param.h>
+
+struct sdram_params params = {
+	.source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG,
+	.frequency = 1600,
+	.rank_num = 1,
+	.ddr_geometry = DDR_TYPE_2CH_1RK_4GB_4,
+	.wr_level = {
+		[CHANNEL_A] = { {0x1F, 0x19}, {0x20, 0x1A} },
+		[CHANNEL_B] = { {0x22, 0x1E}, {0x22, 0x1E} }
+	},
+	.cbt_cs_dly = {
+		[CHANNEL_A] = {0x5, 0x4},
+		[CHANNEL_B] = {0x8, 0x8}
+	},
+	.cbt_final_vref = {
+		[CHANNEL_A] = {0x56, 0x56},
+		[CHANNEL_B] = {0x56, 0x56}
+	},
+	.emi_cona_val = 0xF053F154,
+	.emi_conh_val = 0x44440003,
+	.emi_conf_val = 0x00421000,
+	.chn_emi_cona_val = {0x0444F051, 0x0444F051},
+	.cbt_mode_extern = CBT_NORMAL_MODE,
+	.delay_cell_unit = 868,
+};

src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c

@@ -5,6 +5,7 @@
 struct sdram_params params = {
 	.source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG,
 	.frequency = 1600,
+	.rank_num = 2,
 	.ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2,
 	.wr_level = {
 		[CHANNEL_A] = { {0x1F, 0x19}, {0x20, 0x1A} },

src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E2G32D4NQ-046-8GB.c

@@ -6,6 +6,7 @@ struct sdram_params params = {
 	.source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG,
 	.ddr_geometry = DDR_TYPE_2CH_2RK_8GB_4_4,
 	.frequency = 1600,
+	.rank_num = 2,
 	.wr_level = {
 		[CHANNEL_A] = { {0x1F, 0x19}, {0x20, 0x1A} },
 		[CHANNEL_B] = { {0x22, 0x1E}, {0x22, 0x1E} }

src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c

@@ -5,6 +5,7 @@
 struct sdram_params params = {
 	.source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG,
 	.frequency = 1600,
+	.rank_num = 2,
 	.ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2,
 	.wr_level = {
 		[CHANNEL_A] = { {0x1F, 0x1C}, {0x1C, 0x1B} },