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mainboard/hp: Add Elitebook Folio 9470m 

The code is based on autoport and that for revolve_810g1

Tested:
- CPU i5-3437U
- Slotted DIMM 8GiB
- Onboard USB2 interfaces (wlan slot, wwan slot, camera, smart card)
- Mini pci-e on wlan slot
- On board SDHCI connected to pci-e
- USB3 ports
- USB3 hub on dock (connected to USB3 port 1)
- NVRAM options for North and South bridges
- S3
- TPM1 on LPC
- Linux 4.13.17-1 within Debian GNU/Linux testing, loaded from
  SeaBIOS, or Linux payload (Heads)

Not tested:
- Fingerprint reader on USB2

Not working well:
- EHCI debug on port SSP2,(The USB port on the left, wired to ehci
  before OS) it has always-on enabled by default (maybe via EC),
  which disturbs FT232H's own power up, requiring a very critical
  timing to plug it in for it to work.

Change-Id: I52e549ec18e8aa661a506a16dbc7f83417c0da78
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/25218
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Bill XIE 2018-03-15 20:05:35 +08:00 committed by Patrick Georgi
parent 2c1cdea413
commit 7693c94ecf
16 changed files with 904 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

63
src/mainboard/hp/folio_9470m/Kconfig Normal file
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if BOARD_HP_FOLIO_9470M
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select BOARD_ROMSIZE_KB_16384
select CPU_INTEL_SOCKET_RPGA989
select EC_HP_KBC1126
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select INTEL_INT15
select NORTHBRIDGE_INTEL_IVYBRIDGE
select SANDYBRIDGE_IVYBRIDGE_LVDS
select SERIRQ_CONTINUOUS_MODE
select SOUTHBRIDGE_INTEL_C216
select SYSTEM_TYPE_LAPTOP
select USE_NATIVE_RAMINIT
select MAINBOARD_HAS_LPC_TPM
select HAVE_OPTION_TABLE
select HAVE_CMOS_DEFAULT
select ENABLE_VMX
select MAINBOARD_HAS_LIBGFXINIT
select GFX_GMA_INTERNAL_IS_LVDS
config HAVE_IFD_BIN
bool
default n
config HAVE_ME_BIN
bool
default n
config MAINBOARD_DIR
string
default hp/folio_9470m
config MAINBOARD_PART_NUMBER
string
default "EliteBook Folio 9470m"
config VGA_BIOS_FILE
string
default "pci8086,0166.rom"
config VGA_BIOS_ID
string
default "8086,0166"
config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
hex
default 0x18df
config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
hex
default 0x103c
config MAX_CPUS
int
default 8
config USBDEBUG_HCD_INDEX
int
default 0
endif

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src/mainboard/hp/folio_9470m/Kconfig.name Normal file
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config BOARD_HP_FOLIO_9470M
bool "EliteBook Folio 9470m"

18
src/mainboard/hp/folio_9470m/Makefile.inc Normal file
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##
## This file is part of the coreboot project.
##
## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
romstage-y += gpio.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

16
src/mainboard/hp/folio_9470m/acpi/ec.asl Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <ec/hp/kbc1126/acpi/ec.asl>

27
src/mainboard/hp/folio_9470m/acpi/platform.asl Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
Method(_WAK,1)
{
\_SB.PCI0.LPCB.EC0.ACPI = 1
\_SB.PCI0.LPCB.EC0.SLPT = 0
Return(Package(){0,0})
}
Method(_PTS,1)
{
\_SB.PCI0.LPCB.EC0.SLPT = Arg0
}

1
src/mainboard/hp/folio_9470m/acpi/superio.asl Normal file
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#include <drivers/pc80/pc/ps2_controller.asl>

35
src/mainboard/hp/folio_9470m/acpi_tables.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008-2009 coresystems GmbH
* Copyright (C) 2014 Vladimir Serbinenko
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <southbridge/intel/bd82x6x/nvs.h>
void acpi_create_gnvs(global_nvs_t *gnvs)
{
/* Disable USB ports in S3 by default */
gnvs->s3u0 = 0;
gnvs->s3u1 = 0;
/* Disable USB ports in S5 by default */
gnvs->s5u0 = 0;
gnvs->s5u1 = 0;
// the lid is open by default.
gnvs->lids = 1;
gnvs->tcrt = 100;
gnvs->tpsv = 90;
}

7
src/mainboard/hp/folio_9470m/board_info.txt Normal file
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Category: laptop
Board URL: https://support.hp.com/us-en/product/hp-elitebook-folio-9470m-ultrabook/5271146/product-info
ROM package: SOIC-8
ROM protocol: SPI
ROM socketed: n
Flashrom support: n
Release year: 2013

6
src/mainboard/hp/folio_9470m/cmos.default Normal file
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boot_option=Fallback
debug_level=Spew
power_on_after_fail=Disable
nmi=Enable
volume=0x3
gfx_uma_size=32M

116
src/mainboard/hp/folio_9470m/cmos.layout Normal file
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##
## This file is part of the coreboot project.
##
## Copyright (C) 2007-2008 coresystems GmbH
## Copyright (C) 2014 Vladimir Serbinenko
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
# -----------------------------------------------------------------
entries
# -----------------------------------------------------------------
# Status Register A
# -----------------------------------------------------------------
# Status Register B
# -----------------------------------------------------------------
# Status Register C
#96 4 r 0 status_c_rsvd
#100 1 r 0 uf_flag
#101 1 r 0 af_flag
#102 1 r 0 pf_flag
#103 1 r 0 irqf_flag
# -----------------------------------------------------------------
# Status Register D
#104 7 r 0 status_d_rsvd
#111 1 r 0 valid_cmos_ram
# -----------------------------------------------------------------
# Diagnostic Status Register
#112 8 r 0 diag_rsvd1
# -----------------------------------------------------------------
0 120 r 0 reserved_memory
#120 264 r 0 unused
# -----------------------------------------------------------------
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 4 boot_option
388 4 h 0 reboot_counter
#390 2 r 0 unused?
# -----------------------------------------------------------------
# coreboot config options: console
#392 3 r 0 unused
395 4 e 6 debug_level
#399 1 r 0 unused
#400 8 r 0 reserved for century byte
# coreboot config options: southbridge
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
421 1 e 9 sata_mode
# coreboot config options: cpu
#424 8 r 0 unused
# coreboot config options: northbridge
432 3 e 11 gfx_uma_size
#435 5 r 0 unused
440 8 h 0 volume
# SandyBridge MRC Scrambler Seed values
896 32 r 0 mrc_scrambler_seed
928 32 r 0 mrc_scrambler_seed_s3
960 16 r 0 mrc_scrambler_seed_chk
# coreboot config options: check sums
984 16 h 0 check_sum
# -----------------------------------------------------------------
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
7 0 Disable
7 1 Enable
7 2 Keep
9 0 AHCI
9 1 Compatible
11 0 32M
11 1 64M
11 2 96M
11 3 128M
11 4 160M
11 5 192M
11 6 224M
# -----------------------------------------------------------------
checksums
checksum 392 447 984

148
src/mainboard/hp/folio_9470m/devicetree.cb Normal file
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#
# This file is part of the coreboot project.
#
# Copyright (C) 2018 Bill Xie <persmule@gmail.com>
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did
register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
register "gfx.link_frequency_270_mhz" = "1"
register "gfx.ndid" = "3"
register "gfx.use_spread_spectrum_clock" = "1"
register "gpu_cpu_backlight" = "0x00000d9c"
register "gpu_dp_b_hotplug" = "4"
register "gpu_dp_c_hotplug" = "4"
register "gpu_dp_d_hotplug" = "4"
register "gpu_panel_port_select" = "0"
register "gpu_panel_power_backlight_off_delay" = "2000"
register "gpu_panel_power_backlight_on_delay" = "2000"
register "gpu_panel_power_cycle_delay" = "5"
register "gpu_panel_power_down_delay" = "230"
register "gpu_panel_power_up_delay" = "300"
register "gpu_pch_backlight" = "0x0d9c0d9c"
device cpu_cluster 0x0 on
chip cpu/intel/socket_rPGA989
device lapic 0x0 on
end
end
chip cpu/intel/model_206ax # FIXME: check all registers
register "c1_acpower" = "1"
register "c1_battery" = "1"
register "c2_acpower" = "3"
register "c2_battery" = "3"
register "c3_acpower" = "5"
register "c3_battery" = "5"
device lapic 0xacac off
end
end
end
device domain 0x0 on
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"
register "docking_supported" = "0"
register "gen1_dec" = "0x007c0201"
register "gen2_dec" = "0x000c0101"
register "gen3_dec" = "0x00fcfe01"
register "gen4_dec" = "0x000402e9"
register "gpi6_routing" = "2"
register "p_cnt_throttling_supported" = "1"
register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
register "pcie_port_coalesce" = "1"
register "sata_interface_speed_support" = "0x3"
register "sata_port_map" = "0x3"
register "spi_lvscc" = "0x0"
register "spi_uvscc" = "0x2005"
register "superspeed_capable_ports" = "0x0000000f"
register "xhci_overcurrent_mapping" = "0x00000c03"
register "xhci_switchable_ports" = "0x0000000f"
device pci 14.0 on # USB 3.0 Controller
subsystemid 0x103c 0x18df
end
device pci 16.0 off # Management Engine Interface 1
subsystemid 0x103c 0x18df
end
device pci 16.1 off # Management Engine Interface 2
end
device pci 16.2 off # Management Engine IDE-R
end
device pci 16.3 off # Management Engine KT
subsystemid 0x103c 0x18df
end
device pci 19.0 on # Intel Gigabit Ethernet
subsystemid 0x103c 0x18df
end
device pci 1a.0 on # USB2 EHCI #2
subsystemid 0x103c 0x18df
end
device pci 1b.0 on # High Definition Audio Audio controller
subsystemid 0x103c 0x18df
end
device pci 1c.0 on # PCIe Port #1
subsystemid 0x103c 0x18df
end
device pci 1c.1 off # PCIe Port #2
end
device pci 1c.2 on # PCIe Port #3
subsystemid 0x103c 0x18df
end # SDHCI
device pci 1c.3 on # PCIe Port #4
subsystemid 0x103c 0x18df
end # WLAN
device pci 1c.4 off # PCIe Port #5
end
device pci 1c.5 off # PCIe Port #6
end
device pci 1c.6 off # PCIe Port #7
end
device pci 1c.7 off # PCIe Port #8
end
device pci 1d.0 on # USB2 EHCI #1
subsystemid 0x103c 0x18df
end
device pci 1e.0 off # PCI bridge
end
device pci 1f.0 on # LPC bridge PCI-LPC bridge
subsystemid 0x103c 0x18df
chip ec/hp/kbc1126
register "ec_data_port" = "0x62"
register "ec_cmd_port" = "0x66"
register "ec_ctrl_reg" = "0x81"
register "ec_fan_ctrl_value" = "0x44"
device pnp ff.1 off end
end # kbc1126
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
end
device pci 1f.2 on # SATA Controller 1
subsystemid 0x103c 0x18df
end
device pci 1f.3 on # SMBus
subsystemid 0x103c 0x18df
end
device pci 1f.5 off # SATA Controller 2
end
device pci 1f.6 off # Thermal
end
end
device pci 00.0 on # Host bridge Host bridge
subsystemid 0x103c 0x18df
end
device pci 01.0 off # PCIe Bridge for discrete graphics
end
device pci 02.0 on # Internal graphics VGA controller
subsystemid 0x103c 0x18df
end
end
end

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src/mainboard/hp/folio_9470m/dsdt.asl Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
DefinitionBlock(
"dsdt.aml",
"DSDT",
0x03, // DSDT revision: ACPI v3.0
"COREv4", // OEM id
"COREBOOT", // OEM table id
0x20141018 // OEM revision
)
{
// Some generic macros
#include "acpi/platform.asl"
#include <cpu/intel/model_206ax/acpi/cpu.asl>
#include <southbridge/intel/bd82x6x/acpi/platform.asl>
/* global NVS and variables. */
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
#include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
Scope (\_SB) {
Device (PCI0)
{
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
}
}
}

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src/mainboard/hp/folio_9470m/gpio.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008-2009 coresystems GmbH
* Copyright (C) 2014 Vladimir Serbinenko
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <southbridge/intel/common/gpio.h>
static const struct pch_gpio_set1 pch_gpio_set1_mode = {
.gpio0 = GPIO_MODE_GPIO,
.gpio1 = GPIO_MODE_GPIO,
.gpio2 = GPIO_MODE_GPIO,
.gpio3 = GPIO_MODE_GPIO,
.gpio4 = GPIO_MODE_GPIO,
.gpio5 = GPIO_MODE_NATIVE,
.gpio6 = GPIO_MODE_GPIO,
.gpio7 = GPIO_MODE_GPIO,
.gpio8 = GPIO_MODE_GPIO,
.gpio9 = GPIO_MODE_GPIO,
.gpio10 = GPIO_MODE_GPIO,
.gpio11 = GPIO_MODE_GPIO,
.gpio12 = GPIO_MODE_NATIVE,
.gpio13 = GPIO_MODE_GPIO,
.gpio14 = GPIO_MODE_GPIO,
.gpio15 = GPIO_MODE_GPIO,
.gpio16 = GPIO_MODE_GPIO,
.gpio17 = GPIO_MODE_GPIO,
.gpio18 = GPIO_MODE_GPIO,
.gpio19 = GPIO_MODE_GPIO,
.gpio20 = GPIO_MODE_GPIO,
.gpio21 = GPIO_MODE_GPIO,
.gpio22 = GPIO_MODE_GPIO,
.gpio23 = GPIO_MODE_GPIO,
.gpio24 = GPIO_MODE_GPIO,
.gpio25 = GPIO_MODE_NATIVE,
.gpio26 = GPIO_MODE_NATIVE,
.gpio27 = GPIO_MODE_GPIO,
.gpio28 = GPIO_MODE_GPIO,
.gpio29 = GPIO_MODE_GPIO,
.gpio30 = GPIO_MODE_NATIVE,
.gpio31 = GPIO_MODE_NATIVE,
};
static const struct pch_gpio_set1 pch_gpio_set1_direction = {
.gpio0 = GPIO_DIR_OUTPUT,
.gpio1 = GPIO_DIR_INPUT,
.gpio2 = GPIO_DIR_OUTPUT,
.gpio3 = GPIO_DIR_OUTPUT,
.gpio4 = GPIO_DIR_INPUT,
.gpio6 = GPIO_DIR_INPUT,
.gpio7 = GPIO_DIR_INPUT,
.gpio8 = GPIO_DIR_INPUT,
.gpio9 = GPIO_DIR_INPUT,
.gpio10 = GPIO_DIR_INPUT,
.gpio11 = GPIO_DIR_OUTPUT,
.gpio13 = GPIO_DIR_INPUT,
.gpio14 = GPIO_DIR_INPUT,
.gpio15 = GPIO_DIR_INPUT,
.gpio16 = GPIO_DIR_INPUT,
.gpio17 = GPIO_DIR_INPUT,
.gpio18 = GPIO_DIR_INPUT,
.gpio19 = GPIO_DIR_INPUT,
.gpio20 = GPIO_DIR_INPUT,
.gpio21 = GPIO_DIR_INPUT,
.gpio22 = GPIO_DIR_OUTPUT,
.gpio23 = GPIO_DIR_INPUT,
.gpio24 = GPIO_DIR_INPUT,
.gpio27 = GPIO_DIR_INPUT,
.gpio28 = GPIO_DIR_INPUT,
.gpio29 = GPIO_DIR_OUTPUT,
};
static const struct pch_gpio_set1 pch_gpio_set1_level = {
.gpio0 = GPIO_LEVEL_LOW,
.gpio2 = GPIO_LEVEL_HIGH,
.gpio3 = GPIO_LEVEL_LOW,
.gpio11 = GPIO_LEVEL_LOW,
.gpio22 = GPIO_LEVEL_HIGH,
.gpio29 = GPIO_LEVEL_HIGH,
};
static const struct pch_gpio_set1 pch_gpio_set1_reset = {
.gpio24 = GPIO_RESET_RSMRST,
.gpio30 = GPIO_RESET_RSMRST,
};
static const struct pch_gpio_set1 pch_gpio_set1_invert = {
.gpio1 = GPIO_INVERT,
.gpio4 = GPIO_INVERT,
.gpio6 = GPIO_INVERT,
.gpio7 = GPIO_INVERT,
};
static const struct pch_gpio_set1 pch_gpio_set1_blink = {
};
static const struct pch_gpio_set2 pch_gpio_set2_mode = {
.gpio32 = GPIO_MODE_NATIVE,
.gpio33 = GPIO_MODE_GPIO,
.gpio34 = GPIO_MODE_GPIO,
.gpio35 = GPIO_MODE_GPIO,
.gpio36 = GPIO_MODE_GPIO,
.gpio37 = GPIO_MODE_GPIO,
.gpio38 = GPIO_MODE_GPIO,
.gpio39 = GPIO_MODE_GPIO,
.gpio40 = GPIO_MODE_GPIO,
.gpio41 = GPIO_MODE_GPIO,
.gpio42 = GPIO_MODE_GPIO,
.gpio43 = GPIO_MODE_GPIO,
.gpio44 = GPIO_MODE_GPIO,
.gpio45 = GPIO_MODE_NATIVE,
.gpio46 = GPIO_MODE_GPIO,
.gpio47 = GPIO_MODE_GPIO,
.gpio48 = GPIO_MODE_GPIO,
.gpio49 = GPIO_MODE_GPIO,
.gpio50 = GPIO_MODE_GPIO,
.gpio51 = GPIO_MODE_GPIO,
.gpio52 = GPIO_MODE_GPIO,
.gpio53 = GPIO_MODE_GPIO,
.gpio54 = GPIO_MODE_GPIO,
.gpio55 = GPIO_MODE_GPIO,
.gpio56 = GPIO_MODE_GPIO,
.gpio57 = GPIO_MODE_GPIO,
.gpio58 = GPIO_MODE_NATIVE,
.gpio59 = GPIO_MODE_GPIO,
.gpio60 = GPIO_MODE_GPIO,
.gpio61 = GPIO_MODE_GPIO,
.gpio62 = GPIO_MODE_NATIVE,
.gpio63 = GPIO_MODE_NATIVE,
};
static const struct pch_gpio_set2 pch_gpio_set2_direction = {
.gpio33 = GPIO_DIR_OUTPUT,
.gpio34 = GPIO_DIR_INPUT,
.gpio35 = GPIO_DIR_INPUT,
.gpio36 = GPIO_DIR_INPUT,
.gpio37 = GPIO_DIR_INPUT,
.gpio38 = GPIO_DIR_INPUT,
.gpio39 = GPIO_DIR_INPUT,
.gpio40 = GPIO_DIR_INPUT,
.gpio41 = GPIO_DIR_INPUT,
.gpio42 = GPIO_DIR_INPUT,
.gpio43 = GPIO_DIR_INPUT,
.gpio44 = GPIO_DIR_INPUT,
.gpio46 = GPIO_DIR_INPUT,
.gpio47 = GPIO_DIR_INPUT,
.gpio48 = GPIO_DIR_INPUT,
.gpio49 = GPIO_DIR_INPUT,
.gpio50 = GPIO_DIR_INPUT,
.gpio51 = GPIO_DIR_INPUT,
.gpio52 = GPIO_DIR_INPUT,
.gpio53 = GPIO_DIR_OUTPUT,
.gpio54 = GPIO_DIR_INPUT,
.gpio55 = GPIO_DIR_INPUT,
.gpio56 = GPIO_DIR_INPUT,
.gpio57 = GPIO_DIR_OUTPUT,
.gpio59 = GPIO_DIR_INPUT,
.gpio60 = GPIO_DIR_OUTPUT,
.gpio61 = GPIO_DIR_INPUT,
};
static const struct pch_gpio_set2 pch_gpio_set2_level = {
.gpio33 = GPIO_LEVEL_LOW,
.gpio53 = GPIO_LEVEL_HIGH,
.gpio57 = GPIO_LEVEL_HIGH,
.gpio60 = GPIO_LEVEL_HIGH,
};
static const struct pch_gpio_set2 pch_gpio_set2_reset = {
};
static const struct pch_gpio_set3 pch_gpio_set3_mode = {
.gpio64 = GPIO_MODE_GPIO,
.gpio65 = GPIO_MODE_GPIO,
.gpio66 = GPIO_MODE_GPIO,
.gpio67 = GPIO_MODE_GPIO,
.gpio68 = GPIO_MODE_GPIO,
.gpio69 = GPIO_MODE_GPIO,
.gpio70 = GPIO_MODE_GPIO,
.gpio71 = GPIO_MODE_GPIO,
.gpio72 = GPIO_MODE_GPIO,
.gpio73 = GPIO_MODE_NATIVE,
.gpio74 = GPIO_MODE_NATIVE,
.gpio75 = GPIO_MODE_NATIVE,
};
static const struct pch_gpio_set3 pch_gpio_set3_direction = {
.gpio64 = GPIO_DIR_INPUT,
.gpio65 = GPIO_DIR_INPUT,
.gpio66 = GPIO_DIR_INPUT,
.gpio67 = GPIO_DIR_INPUT,
.gpio68 = GPIO_DIR_INPUT,
.gpio69 = GPIO_DIR_INPUT,
.gpio70 = GPIO_DIR_OUTPUT,
.gpio71 = GPIO_DIR_OUTPUT,
.gpio72 = GPIO_DIR_OUTPUT,
};
static const struct pch_gpio_set3 pch_gpio_set3_level = {
.gpio70 = GPIO_LEVEL_HIGH,
.gpio71 = GPIO_LEVEL_HIGH,
.gpio72 = GPIO_LEVEL_LOW,
};
static const struct pch_gpio_set3 pch_gpio_set3_reset = {
};
const struct pch_gpio_map mainboard_gpio_map = {
.set1 = {
.mode = &pch_gpio_set1_mode,
.direction = &pch_gpio_set1_direction,
.level = &pch_gpio_set1_level,
.blink = &pch_gpio_set1_blink,
.invert = &pch_gpio_set1_invert,
.reset = &pch_gpio_set1_reset,
},
.set2 = {
.mode = &pch_gpio_set2_mode,
.direction = &pch_gpio_set2_direction,
.level = &pch_gpio_set2_level,
.reset = &pch_gpio_set2_reset,
},
.set3 = {
.mode = &pch_gpio_set3_mode,
.direction = &pch_gpio_set3_direction,
.level = &pch_gpio_set3_level,
.reset = &pch_gpio_set3_reset,
},
};

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008-2009 coresystems GmbH
* Copyright (C) 2014 Vladimir Serbinenko
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
0x111d76e0, /* Codec Vendor / Device ID: IDT */
0x103c18df, /* Subsystem ID */
0x0000000b, /* Number of 4 dword sets */
/* NID 0x01: Subsystem ID. */
AZALIA_SUBVENDOR(0x0, 0x103c18df),
/* NID 0x0a. */
AZALIA_PIN_CFG(0x0, 0x0a, 0x21011030),
/* NID 0x0b. */
AZALIA_PIN_CFG(0x0, 0x0b, 0x0321101f),
/* NID 0x0c. */
AZALIA_PIN_CFG(0x0, 0x0c, 0x03a11020),
/* NID 0x0d. */
AZALIA_PIN_CFG(0x0, 0x0d, 0x90170110),
/* NID 0x0e. */
AZALIA_PIN_CFG(0x0, 0x0e, 0x40f000f0),
/* NID 0x0f. */
AZALIA_PIN_CFG(0x0, 0x0f, 0x2181102e),
/* NID 0x10. */
AZALIA_PIN_CFG(0x0, 0x10, 0x40f000f0),
/* NID 0x11. */
AZALIA_PIN_CFG(0x0, 0x11, 0xd5a30140),
/* NID 0x1f. */
AZALIA_PIN_CFG(0x0, 0x1f, 0x40f000f0),
/* NID 0x20. */
AZALIA_PIN_CFG(0x0, 0x20, 0x40f000f0),
0x80862806, /* Codec Vendor / Device ID: Intel */
0x80860101, /* Subsystem ID */
0x00000004, /* Number of 4 dword sets */
/* NID 0x01: Subsystem ID. */
AZALIA_SUBVENDOR(0x3, 0x80860101),
/* NID 0x05. */
AZALIA_PIN_CFG(0x3, 0x05, 0x18560010),
/* NID 0x06. */
AZALIA_PIN_CFG(0x3, 0x06, 0x58560020),
/* NID 0x07. */
AZALIA_PIN_CFG(0x3, 0x07, 0x18560030),
};
const u32 pc_beep_verbs[0] = {};
AZALIA_ARRAY_SIZES;

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2017 Bill Xie <persmule@gmail.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/device.h>
#include <drivers/intel/gma/int15.h>
static void mainboard_enable(device_t dev)
{
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
GMA_INT15_PANEL_FIT_DEFAULT,
GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
}
struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable,
};

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008-2009 coresystems GmbH
* Copyright (C) 2014 Vladimir Serbinenko
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/io.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <ec/hp/kbc1126/ec.h>
void pch_enable_lpc(void)
{
/*
* CNF2 and CNF1 for Super I/O
* MC and LPC (0x60,0x64,0x62,0x66) for KBC and EC
*/
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
/* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201);
}
void mainboard_rcba_config(void)
{
}
const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 1, 0 }, /* SSP1: dock */
{ 1, 1, 0 }, /* SSP2: left, EHCI Debug */
{ 1, 1, 1 }, /* SSP3: right back side */
{ 1, 1, 1 }, /* SSP4: right front side */
{ 1, 0, 2 }, /* B0P5 */
{ 1, 0, 2 }, /* B0P6: wlan USB */
{ 0, 0, 3 }, /* B0P7 */
{ 1, 1, 3 }, /* B0P8: smart card reader */
{ 1, 1, 4 }, /* B1P1: fingerprint reader */
{ 0, 0, 4 }, /* B1P2: (EHCI Debug, not connected) */
{ 1, 1, 5 }, /* B1P3: Camera */
{ 0, 0, 5 }, /* B1P4 */
{ 1, 1, 6 }, /* B1P5: wwan USB */
{ 0, 0, 6 }, /* B1P6 */
};
void mainboard_early_init(int s3resume)
{
}
void mainboard_config_superio(void)
{
kbc1126_enter_conf();
kbc1126_mailbox_init();
kbc1126_kbc_init();
kbc1126_ec_init();
kbc1126_pm1_init();
kbc1126_exit_conf();
}
void mainboard_get_spd(spd_raw_data *spd, bool id_only)
{
read_spd(&spd[0], 0x50, id_only);
read_spd(&spd[2], 0x52, id_only);
}