Enable rom cache early to reduce boot time.
Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6591 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -157,13 +157,6 @@ agesawrapper_amdinitmmio (
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PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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/* Set ROM cache onto WP to decrease post time */
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MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5;
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LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
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MsrReg = (0x1000000000 - CONFIG_ROM_SIZE) | 0x800;
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LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
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Status = AGESA_SUCCESS;
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return (UINT32)Status;
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}
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@ -47,6 +47,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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u32 val;
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u8 reg8;
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// all cores: allow caching of flash chip code and data
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// (there are no cache-as-ram reliability concerns with family 14h)
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__writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5);
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__writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800);
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// all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
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__writemsr (0xc0010062, 0);
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