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mb/google/nissa/var/gothrax: Add GPIO configuration 

Add variant of LTE and WFC support on gothrax board.
We base decisions on the values within the firmware configuration
CBI field.
In fw_config settings, if the board move LTE and WFC modules,
the hardware GPP_A8/GPP_E13/GPP_F12/GPP_H19/GPP_H23/GPP_R6/GPP_R7
pins need to be deasserted.

BUG=b:303526071
TEST=emerge-nissa coreboot & \
Check against schematic.
Whether it works as expected under different SKUs.

Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: Ia8041bdc599509911bde95d6294314036e75b227
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78916
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
This commit is contained in:
Yunlong Jia 2023-11-07 11:13:30 +00:00 committed by Subrata Banik
parent 9a01263952
commit 7698ebe162
3 changed files with 87 additions and 0 deletions
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4
src/mainboard/google/brya/variants/gothrax/Makefile.inc
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@ -4,4 +4,8 @@ bootblock-y += gpio.c
romstage-y += gpio.c
ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
ramstage-y += variant.c
ramstage-y += gpio.c

42
src/mainboard/google/brya/variants/gothrax/fw_config.c Normal file
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@ -0,0 +1,42 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <baseboard/gpio.h>
#include <baseboard/variants.h>
#include <boardid.h>
#include <console/console.h>
#include <fw_config.h>
static const struct pad_config lte_disable_pads_gothrax[] = {
/* A8 : WWAN_RF_DISABLE_ODL */
PAD_NC(GPP_A8, NONE),
/* E13 : WWAN_EN */
PAD_NC_LOCK(GPP_E13, NONE, LOCK_CONFIG),
/* F12 : WWAN_RST_L */
PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG),
/* H19 : SOC_I2C_SUB_INT_ODL */
PAD_NC(GPP_H19, NONE),
/* H23 : WWAN_SAR_DETECT_ODL */
PAD_NC(GPP_H23, NONE),
};
static const struct pad_config wfc_disable_pads[] = {
/* R6 : DMIC_WCAM_CLK_R */
PAD_NC(GPP_R6, NONE),
/* R7 : DMIC_WCAM_DATA */
PAD_NC(GPP_R7, NONE),
};
void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
{
if (!fw_config_probe(FW_CONFIG(DB_USB, DB_C_A_LTE))) {
printk(BIOS_INFO, "Disable LTE-related GPIO pins on gothrax.\n");
gpio_padbased_override(padbased_table, lte_disable_pads_gothrax,
ARRAY_SIZE(lte_disable_pads_gothrax));
}
if (!fw_config_probe(FW_CONFIG(WFC, WFC_PRESENT))) {
printk(BIOS_INFO, "Disable WFC GPIO pins.\n");
gpio_padbased_override(padbased_table, wfc_disable_pads,
ARRAY_SIZE(wfc_disable_pads));
}
}

41
src/mainboard/google/brya/variants/gothrax/variant.c Normal file
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@ -0,0 +1,41 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <baseboard/gpio.h>
#include <baseboard/variants.h>
#include <console/console.h>
#include <fw_config.h>
void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
{
if (!fw_config_probe(FW_CONFIG(DB_USB, DB_C_A_LTE))) {
printk(BIOS_INFO, "Disable usb2_port5 and usb3_port3 of WWAN.\n");
config->usb2_ports[4].enable = 0;
config->usb2_ports[4].ocpin = OC_SKIP;
config->usb2_ports[4].tx_bias = USB2_BIAS_0MV;
config->usb2_ports[4].tx_emp_enable = USB2_EMP_OFF;
config->usb2_ports[4].pre_emp_bias = USB2_BIAS_0MV;
config->usb2_ports[4].pre_emp_bit = USB2_HALF_BIT_PRE_EMP;
config->usb3_ports[2].enable = 0;
config->usb3_ports[2].ocpin = OC_SKIP;
config->usb3_ports[2].tx_de_emp = 0x00;
config->usb3_ports[2].tx_downscale_amp = 0x00;
}
if (!fw_config_probe(FW_CONFIG(WFC, WFC_PRESENT))) {
printk(BIOS_INFO, "Disable usb2_port7 of WFC.\n");
config->usb2_ports[6].enable = 0;
config->usb2_ports[6].ocpin = OC_SKIP;
config->usb2_ports[6].tx_bias = USB2_BIAS_0MV;
config->usb2_ports[6].tx_emp_enable = USB2_EMP_OFF;
config->usb2_ports[6].pre_emp_bias = USB2_BIAS_0MV;
config->usb2_ports[6].pre_emp_bit = USB2_HALF_BIT_PRE_EMP;
}
if (fw_config_probe(FW_CONFIG(DB_USB, DB_A))) {
printk(BIOS_INFO, "Disable typec aux_bias_pads in the SOC.\n");
config->typec_aux_bias_pads[1].pad_auxp_dc = 0x00;
config->typec_aux_bias_pads[1].pad_auxn_dc = 0x00;
}
}