mainboard/google/poppy: Provide baseboard and variant concepts
In order to be able to share code across different poppy variants, provide the concept of baseboard and variants. New directory layout: variants/baseboard - code variants/baseboard/include/baseboard - headers variants/poppy - code variants/poppy/include/variant - headers New boards would then add themselves under their board name within "variants" directory. This is purely an organizational change. BUG=b:37375693 Change-Id: If6c1c5f479cfffe768abf27495d379744104e2dc Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19322 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -18,6 +18,10 @@ config BOARD_GOOGLE_BASEBOARD_POPPY
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if BOARD_GOOGLE_BASEBOARD_POPPY
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config DEVICETREE
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string
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default "variants/baseboard/devicetree.cb"
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config DRIVER_TPM_SPI_BUS
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default 0x1
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@ -59,6 +63,10 @@ config POPPY_USE_SPI_TPM
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select SPI_TPM
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select TPM2
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config VARIANT_DIR
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string
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default "poppy" if BOARD_GOOGLE_POPPY
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config VBOOT
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select EC_GOOGLE_CHROMEEC_SWITCHES
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select VBOOT_LID_SWITCH
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@ -30,3 +30,9 @@ ramstage-y += mainboard.c
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ramstage-y += ramstage.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
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subdirs-y += variants/baseboard
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
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subdirs-y += variants/$(VARIANT_DIR)
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
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@ -16,7 +16,7 @@
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#include <bootblock_common.h>
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#include <soc/gpio.h>
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#include "gpio.h"
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#include <variant/gpio.h>
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static void early_config_gpio(void)
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{
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@ -21,7 +21,7 @@
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#include <tpm.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include "gpio.h"
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#include <variant/gpio.h>
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#if ENV_RAMSTAGE
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#include <boot/coreboot_tables.h>
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@ -13,8 +13,8 @@
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* GNU General Public License for more details.
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*/
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#include "ec.h"
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#include "gpio.h"
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#include <variant/ec.h>
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#include <variant/gpio.h>
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DefinitionBlock(
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"dsdt.aml",
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@ -67,6 +67,6 @@ DefinitionBlock(
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Scope (\_SB)
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{
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/* Dynamic Platform Thermal Framework */
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#include "acpi/dptf.asl"
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#include <variant/acpi/dptf.asl>
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}
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}
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@ -16,7 +16,7 @@
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#include <arch/acpi.h>
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#include <ec/google/chromeec/ec.h>
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#include "ec.h"
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#include <variant/ec.h>
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void mainboard_ec_init(void)
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{
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@ -15,7 +15,7 @@
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#include <soc/ramstage.h>
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#include "gpio.h"
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#include <variant/gpio.h>
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void mainboard_silicon_init_params(FSP_SIL_UPD *params)
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{
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@ -17,7 +17,7 @@
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#include <ec/google/chromeec/smm.h>
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#include <soc/smm.h>
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#include "ec.h"
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#include <variant/ec.h>
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void mainboard_smi_espi_handler(void)
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{
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@ -23,7 +23,7 @@
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#include <soc/romstage.h>
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#include <string.h>
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#include "../gpio.h"
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#include <variant/gpio.h>
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#include "spd.h"
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static void mainboard_print_spd_info(uint8_t spd[])
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@ -13,13 +13,13 @@
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* GNU General Public License for more details.
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*/
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#ifndef __MAINBOARD_EC_H__
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#define __MAINBOARD_EC_H__
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#ifndef __BASEBOARD_EC_H__
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#define __BASEBOARD_EC_H__
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#include <ec/ec.h>
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#include <ec/google/chromeec/ec_commands.h>
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#include "gpio.h"
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#include <variant/gpio.h>
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#define MAINBOARD_EC_SCI_EVENTS \
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(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
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@ -13,8 +13,8 @@
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* GNU General Public License for more details.
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*/
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#ifndef __MAINBOARD_GPIO_H__
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#define __MAINBOARD_GPIO_H__
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#ifndef __BASEBOARD_GPIO_H__
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#define __BASEBOARD_GPIO_H__
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#include <soc/gpe.h>
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#include <soc/gpio.h>
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@ -396,6 +396,6 @@ static const struct pad_config early_gpio_table[] = {
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PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST),
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};
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#endif
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#endif /* __ACPI__ */
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#endif
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#endif /* BASEBOARD_GPIO_H */
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@ -0,0 +1,16 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2017 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <baseboard/acpi/dptf.asl>
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@ -0,0 +1,21 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2017 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __MAINBOARD_EC_H__
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#define __MAINBOARD_EC_H__
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#include <baseboard/ec.h>
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#endif /* __MAINBOARD_EC_H__ */
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@ -0,0 +1,21 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2017 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
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* GNU General Public License for more details.
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*/
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#ifndef __MAINBOARD_GPIO_H__
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#define __MAINBOARD_GPIO_H__
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#include <baseboard/gpio.h>
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#endif /* __MAINBOARD_GPIO_H__ */
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