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mb/google/corsola: correct NOR flash configuration in GPIO set 

The reference design has changed to use GPIO SET1 for NOR flash.
There are no devices already built using SET0 so we can safely
change the implementation without conditional configs.

Reference document:
kingler_mt8186_mt6366_lpddr4x_e.pdf, page 11.
crab_proto 0_2021112.pdf, page 11.

BUG=b:202871018
TEST=flash verify pass on kingler on bootblock stage

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I031686ccddcf789f3fa966d113ee48949e454b8f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This commit is contained in:
Rex-BC Chen 2021-12-03 14:25:46 +08:00 committed by Hung-Te Lin
parent 9f6805afe8
commit 76c426ab28
1 changed files with 1 additions and 1 deletions
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2
src/mainboard/google/corsola/bootblock.c
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@ -10,7 +10,7 @@ void bootblock_mainboard_init(void)
{
mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0);
mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0);
mtk_snfc_init(SPI_NOR_GPIO_SET0);
mtk_snfc_init(SPI_NOR_GPIO_SET1);
setup_chromeos_gpios();
gpio_eint_configure(GPIO_GSC_AP_INT, IRQ_TYPE_EDGE_RISING);
}