amd/pi/hudson boards: Get rid of power button device
Port commitd7b88dcb
(mb/google/x86-boards: Get rid of power button device in coreboot) to AMD AGESA Hudson boards (SOUTHBRIDGE_AMD_PI_AVALON). The GPE ACPI code seems to originate from commit806def8c
(I missed the svn add on r3787. These are the additional files., Add AMD dbm690t ACPI support.), and was copied over. Change-Id: Ibeec73c15f2282f7ab0be88f96693bcb551b3e45 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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@ -5,7 +5,6 @@ Scope(\_GPE) { /* Start Scope GPE */
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/* General event 3 */
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Method(_L03) {
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/* DBGO("\\_GPE\\_L00\n") */
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Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
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}
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/* Legacy PM event */
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@ -29,7 +28,6 @@ Scope(\_GPE) { /* Start Scope GPE */
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Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
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Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
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Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */
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Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
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}
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/* ExtEvent0 SCI event */
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@ -49,13 +47,11 @@ Scope(\_GPE) { /* Start Scope GPE */
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Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
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Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
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Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
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Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
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}
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/* Azalia SCI event */
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Method(_L1B) {
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/* DBGO("\\_GPE\\_L1B\n") */
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Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
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Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
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}
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} /* End Scope GPE */
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@ -39,13 +39,6 @@ DefinitionBlock (
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/* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
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#include "acpi/routing.asl"
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Device(PWRB) {
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Name(_HID, EISAID("PNP0C0C"))
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Name(_UID, 0xAA)
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Name(_PRW, Package () {3, 0x04})
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Name(_STA, 0x0B)
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}
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Device(PCI0) {
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/* Describe the AMD Northbridge */
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#include <northbridge/amd/pi/00730F01/acpi/northbridge.asl>
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@ -5,7 +5,6 @@ Scope(\_GPE) { /* Start Scope GPE */
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/* General event 3 */
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Method(_L03) {
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/* DBGO("\\_GPE\\_L00\n") */
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Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
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}
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/* Legacy PM event */
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@ -29,7 +28,6 @@ Scope(\_GPE) { /* Start Scope GPE */
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Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
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Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
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Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */
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Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
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}
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/* ExtEvent0 SCI event */
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@ -49,6 +47,5 @@ Scope(\_GPE) { /* Start Scope GPE */
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Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
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Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
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Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
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Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
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}
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} /* End Scope GPE */
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@ -39,13 +39,6 @@ DefinitionBlock (
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/* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
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#include "acpi/routing.asl"
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Device(PWRB) {
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Name(_HID, EISAID("PNP0C0C"))
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Name(_UID, 0xAA)
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Name(_PRW, Package () {3, 0x04})
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Name(_STA, 0x0B)
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}
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Device(PCI0) {
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/* Describe the AMD Northbridge */
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#include <northbridge/amd/pi/00730F01/acpi/northbridge.asl>
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