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amd/pi/hudson boards: Get rid of power button device 

Port commit d7b88dcb (mb/google/x86-boards: Get rid of power button
device in coreboot) to AMD AGESA Hudson boards
(SOUTHBRIDGE_AMD_PI_AVALON).

The GPE ACPI code seems to originate from commit 806def8c (I missed the
svn add on r3787. These are the additional files., Add AMD dbm690t ACPI
support.), and was copied over.

Change-Id: Ibeec73c15f2282f7ab0be88f96693bcb551b3e45
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
This commit is contained in:
Paul Menzel 2020-04-24 18:57:04 +02:00 committed by Patrick Georgi
parent b07e262c48
commit 76d55e5f00
4 changed files with 0 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/mainboard/bap/ode_e21XX/acpi/gpe.asl
View File

@ -5,7 +5,6 @@ Scope(\_GPE) { /* Start Scope GPE */
/* General event 3 */ /* General event 3 */
Method(_L03) { Method(_L03) {
/* DBGO("\\_GPE\\_L00\n") */ /* DBGO("\\_GPE\\_L00\n") */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
} }
/* Legacy PM event */ /* Legacy PM event */
@ -29,7 +28,6 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
} }
/* ExtEvent0 SCI event */ /* ExtEvent0 SCI event */
@ -49,13 +47,11 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
} }
/* Azalia SCI event */ /* Azalia SCI event */
Method(_L1B) { Method(_L1B) {
/* DBGO("\\_GPE\\_L1B\n") */ /* DBGO("\\_GPE\\_L1B\n") */
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
} }
} /* End Scope GPE */ } /* End Scope GPE */

7
src/mainboard/bap/ode_e21XX/dsdt.asl
View File

@ -39,13 +39,6 @@ DefinitionBlock (
/* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
#include "acpi/routing.asl" #include "acpi/routing.asl"
Device(PWRB) {
Name(_HID, EISAID("PNP0C0C"))
Name(_UID, 0xAA)
Name(_PRW, Package () {3, 0x04})
Name(_STA, 0x0B)
}
Device(PCI0) { Device(PCI0) {
/* Describe the AMD Northbridge */ /* Describe the AMD Northbridge */
#include <northbridge/amd/pi/00730F01/acpi/northbridge.asl> #include <northbridge/amd/pi/00730F01/acpi/northbridge.asl>

3
src/mainboard/pcengines/apu2/acpi/gpe.asl
View File

@ -5,7 +5,6 @@ Scope(\_GPE) { /* Start Scope GPE */
/* General event 3 */ /* General event 3 */
Method(_L03) { Method(_L03) {
/* DBGO("\\_GPE\\_L00\n") */ /* DBGO("\\_GPE\\_L00\n") */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
} }
/* Legacy PM event */ /* Legacy PM event */
@ -29,7 +28,6 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
} }
/* ExtEvent0 SCI event */ /* ExtEvent0 SCI event */
@ -49,6 +47,5 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
} }
} /* End Scope GPE */ } /* End Scope GPE */

7
src/mainboard/pcengines/apu2/dsdt.asl
View File

@ -39,13 +39,6 @@ DefinitionBlock (
/* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
#include "acpi/routing.asl" #include "acpi/routing.asl"
Device(PWRB) {
Name(_HID, EISAID("PNP0C0C"))
Name(_UID, 0xAA)
Name(_PRW, Package () {3, 0x04})
Name(_STA, 0x0B)
}
Device(PCI0) { Device(PCI0) {
/* Describe the AMD Northbridge */ /* Describe the AMD Northbridge */
#include <northbridge/amd/pi/00730F01/acpi/northbridge.asl> #include <northbridge/amd/pi/00730F01/acpi/northbridge.asl>