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mainboard/*: Convert to generic ITE superio romstage component 

Convert mainboard's that use model specific romstage functions of
it8712f to the generic framework by following the reasoning of:

a7d14a1 ite/common: Introduce common watchdog and 3.3V VSB helpers

Change-Id: I1485306a951103c9a4bc0dbe87c416c91f46c36f
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5737
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
This commit is contained in:
Edward O'Callaghan 2014-05-14 19:15:08 +10:00 committed by Marc Jones
parent 470c37c372
commit 76d8fd6095
7 changed files with 16 additions and 11 deletions
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6
src/mainboard/asus/m2v-mx_se/romstage.c
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@ -46,7 +46,7 @@ unsigned int get_sbdn(unsigned bus);
#include <spd.h> #include <spd.h>
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
#define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO) #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO)
static void memreset(int controllers, const struct mem_controller *ctrl) { } static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { }
@ -129,8 +129,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
struct sys_info *sysinfo = &sysinfo_car; struct sys_info *sysinfo = &sysinfo_car;
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
it8712f_kill_watchdog(); ite_kill_watchdog(GPIO_DEV);
it8712f_enable_3vsbsw(); ite_enable_3vsbsw(GPIO_DEV);
console_init(); console_init();
enable_rom_decode(); enable_rom_decode();

6
src/mainboard/asus/m2v/romstage.c
View File

@ -46,7 +46,7 @@ unsigned int get_sbdn(unsigned bus);
#include <spd.h> #include <spd.h>
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
#define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO) #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO)
#define CLKIN_DEV PNP_DEV(0x2e, IT8712F_GPIO) #define CLKIN_DEV PNP_DEV(0x2e, IT8712F_GPIO)
#define IT8712F_GPIO_BASE 0x0a20 #define IT8712F_GPIO_BASE 0x0a20
@ -227,12 +227,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24); ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24);
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
it8712f_kill_watchdog(); ite_kill_watchdog(GPIO_DEV);
console_init(); console_init();
enable_rom_decode(); enable_rom_decode();
m2v_bus_init(); m2v_bus_init();
m2v_it8712f_gpio_init(); m2v_it8712f_gpio_init();
it8712f_enable_3vsbsw(); ite_enable_3vsbsw(GPIO_DEV);
printk(BIOS_INFO, "now booting... \n"); printk(BIOS_INFO, "now booting... \n");

3
src/mainboard/asus/m4a78-em/romstage.c
View File

@ -51,6 +51,7 @@
#include "northbridge/amd/amdfam10/debug.c" #include "northbridge/amd/amdfam10/debug.c"
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO)
static void activate_spd_rom(const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { }
@ -99,7 +100,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sb7xx_51xx_lpc_init(); sb7xx_51xx_lpc_init();
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
it8712f_kill_watchdog(); ite_kill_watchdog(GPIO_DEV);
console_init(); console_init();

3
src/mainboard/asus/m4a785-m/romstage.c
View File

@ -51,6 +51,7 @@
#include "northbridge/amd/amdfam10/debug.c" #include "northbridge/amd/amdfam10/debug.c"
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO)
static void activate_spd_rom(const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { }
@ -99,7 +100,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sb7xx_51xx_lpc_init(); sb7xx_51xx_lpc_init();
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
it8712f_kill_watchdog(); ite_kill_watchdog(GPIO_DEV);
console_init(); console_init();

3
src/mainboard/siemens/sitemp_g1p1/romstage.c
View File

@ -47,6 +47,7 @@
#include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */ #include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO)
/* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/ /* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
static void memreset(int controllers, const struct mem_controller *ctrl) static void memreset(int controllers, const struct mem_controller *ctrl)
@ -107,7 +108,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
check_cmos(); // rebooting in case of corrupted cmos !!!!! check_cmos(); // rebooting in case of corrupted cmos !!!!!
#endif #endif
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
it8712f_kill_watchdog(); ite_kill_watchdog(GPIO_DEV);
console_init(); console_init();
#if defined(DUMP_CMOS_RAM) && (DUMP_CMOS_RAM == 1) #if defined(DUMP_CMOS_RAM) && (DUMP_CMOS_RAM == 1)

3
src/mainboard/technexion/tim5690/romstage.c
View File

@ -40,6 +40,7 @@
#include "southbridge/amd/sb600/early_setup.c" #include "southbridge/amd/sb600/early_setup.c"
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO)
static void memreset(int controllers, const struct mem_controller *ctrl) { } static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { }
@ -89,7 +90,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sb600_lpc_init(); sb600_lpc_init();
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
it8712f_kill_watchdog(); ite_kill_watchdog(GPIO_DEV);
console_init(); console_init();

3
src/mainboard/technexion/tim8690/romstage.c
View File

@ -40,6 +40,7 @@
#include "southbridge/amd/sb600/early_setup.c" #include "southbridge/amd/sb600/early_setup.c"
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO)
static void memreset(int controllers, const struct mem_controller *ctrl) { } static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { }
@ -84,7 +85,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sb600_lpc_init(); sb600_lpc_init();
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
it8712f_kill_watchdog(); ite_kill_watchdog(GPIO_DEV);
console_init(); console_init();