nb/intel/haswell: Limit mainboard USB config array lengths
There are at most 14 USB2 ports and 6 USB3 ports on LynxPoint-H, and there are at most 10 USB2 ports and 4 USB3 ports on LynxPoint-LP. Limit the array lengths accordingly to cause build errors on invalid configs. Change-Id: Ieda7a1320d78dbbcb651f1715a87cd1d202a79f2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51451 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -10,8 +10,6 @@ typedef void (*tx_byte_func)(unsigned char byte);
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#define SPD_LEN 256
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#define SPD_LEN 256
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#define MAX_USB2_PORTS 16
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#define MAX_USB3_PORTS 16
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#define USB_OC_PIN_SKIP 8
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#define USB_OC_PIN_SKIP 8
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enum usb2_port_location {
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enum usb2_port_location {
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@ -82,8 +80,8 @@ struct pei_data
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uint32_t max_ddr3_freq;
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uint32_t max_ddr3_freq;
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/* Route all USB ports to XHCI controller in resume path */
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/* Route all USB ports to XHCI controller in resume path */
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int usb_xhci_on_resume;
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int usb_xhci_on_resume;
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struct usb2_port_setting usb2_ports[MAX_USB2_PORTS];
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struct usb2_port_setting usb2_ports[16];
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struct usb3_port_setting usb3_ports[MAX_USB3_PORTS];
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struct usb3_port_setting usb3_ports[16];
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uint8_t spd_data[4][SPD_LEN];
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uint8_t spd_data[4][SPD_LEN];
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tx_byte_func tx_byte;
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tx_byte_func tx_byte;
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} __packed;
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} __packed;
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@ -13,6 +13,14 @@ struct spd_info {
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unsigned int spd_index;
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unsigned int spd_index;
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};
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};
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#if CONFIG(INTEL_LYNXPOINT_LP)
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#define MAX_USB2_PORTS 10
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#define MAX_USB3_PORTS 4
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#else
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#define MAX_USB2_PORTS 14
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#define MAX_USB3_PORTS 6
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#endif
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/* Mainboard-specific USB configuration */
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/* Mainboard-specific USB configuration */
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extern const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS];
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extern const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS];
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extern const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS];
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extern const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS];
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