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nb/intel/haswell: Limit mainboard USB config array lengths 

There are at most 14 USB2 ports and 6 USB3 ports on LynxPoint-H, and
there are at most 10 USB2 ports and 4 USB3 ports on LynxPoint-LP. Limit
the array lengths accordingly to cause build errors on invalid configs.

Change-Id: Ieda7a1320d78dbbcb651f1715a87cd1d202a79f2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51451
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2021-03-12 18:41:59 +01:00 committed by Patrick Georgi
parent 36714d9fe6
commit 76def38abb
2 changed files with 10 additions and 4 deletions
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6
src/northbridge/intel/haswell/pei_data.h
View File

@ -10,8 +10,6 @@ typedef void (*tx_byte_func)(unsigned char byte);
#define SPD_LEN 256
#define MAX_USB2_PORTS 16
#define MAX_USB3_PORTS 16
#define USB_OC_PIN_SKIP 8
enum usb2_port_location {
@ -82,8 +80,8 @@ struct pei_data
uint32_t max_ddr3_freq;
/* Route all USB ports to XHCI controller in resume path */
int usb_xhci_on_resume;
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS];
struct usb3_port_setting usb3_ports[MAX_USB3_PORTS];
struct usb2_port_setting usb2_ports[16];
struct usb3_port_setting usb3_ports[16];
uint8_t spd_data[4][SPD_LEN];
tx_byte_func tx_byte;
} __packed;

8
src/northbridge/intel/haswell/raminit.h
View File

@ -13,6 +13,14 @@ struct spd_info {
unsigned int spd_index;
};
#if CONFIG(INTEL_LYNXPOINT_LP)
#define MAX_USB2_PORTS 10
#define MAX_USB3_PORTS 4
#else
#define MAX_USB2_PORTS 14
#define MAX_USB3_PORTS 6
#endif
/* Mainboard-specific USB configuration */
extern const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS];
extern const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS];