mb/google/brya: Create ghost4adl variant
Create new variant of Brya "ghost4adl". Memory config and device tree was sourced from the schematics (revision 7670d041f40279b5126990f20ec8f90c0538440c). GPIO overrides have not been added yet. This is to be added in a follow-on CL. BUG=b:234626939 BRANCH=firmware-brya-14505.B TEST=FW_NAME=ghost4adl emerge-brya chromeos-bootimage Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I43c663d700ce8b53248fe203f0becc52610ddb70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
This commit is contained in:
Jack Rosenthal
Felix Held
parent
81d3856755
commit
76ef18d8ff
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@ -113,6 +113,7 @@ config DRIVER_TPM_I2C_BUS
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default 0x1 if BOARD_GOOGLE_BRASK
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default 0x1 if BOARD_GOOGLE_PRIMUS
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default 0x3 if BOARD_GOOGLE_PRIMUS4ES
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default 0x1 if BOARD_GOOGLE_GHOST4ADL
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default 0x1 if BOARD_GOOGLE_GIMBLE
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default 0x3 if BOARD_GOOGLE_GIMBLE4ES
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default 0x1 if BOARD_GOOGLE_REDRIX
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@ -172,6 +173,7 @@ config MAINBOARD_PART_NUMBER
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default "Brask" if BOARD_GOOGLE_BRASK
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default "Primus" if BOARD_GOOGLE_PRIMUS
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default "Primus4ES" if BOARD_GOOGLE_PRIMUS4ES
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default "Ghost4ADL" if BOARD_GOOGLE_GHOST4ADL
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default "Gimble" if BOARD_GOOGLE_GIMBLE
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default "Gimble4ES" if BOARD_GOOGLE_GIMBLE4ES
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default "Redrix" if BOARD_GOOGLE_REDRIX
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@ -204,6 +206,7 @@ config VARIANT_DIR
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default "brask" if BOARD_GOOGLE_BRASK
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default "primus" if BOARD_GOOGLE_PRIMUS
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default "primus4es" if BOARD_GOOGLE_PRIMUS4ES
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default "ghost4adl" if BOARD_GOOGLE_GHOST4ADL
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default "gimble" if BOARD_GOOGLE_GIMBLE
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default "gimble4es" if BOARD_GOOGLE_GIMBLE4ES
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default "redrix" if BOARD_GOOGLE_REDRIX
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@ -57,6 +57,10 @@ config BOARD_GOOGLE_FELWINTER
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select DRIVERS_GENERIC_GPIO_KEYS
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select DRIVERS_GENESYSLOGIC_GL9755
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config BOARD_GOOGLE_GHOST4ADL
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bool "-> Ghost4ADL"
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select BOARD_GOOGLE_BASEBOARD_BRYA
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config BOARD_GOOGLE_GIMBLE
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bool "-> Gimble"
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select BOARD_GOOGLE_BASEBOARD_BRYA
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@ -0,0 +1,2 @@
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# SPDX-License-Identifier: GPL-2.0-only
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romstage-y += memory.c
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@ -0,0 +1,8 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef __VARIANT_EC_H__
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#define __VARIANT_EC_H__
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#include <baseboard/ec.h>
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#endif
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@ -0,0 +1,8 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef VARIANT_GPIO_H
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#define VARIANT_GPIO_H
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#include <baseboard/gpio.h>
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#endif
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@ -0,0 +1,118 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <gpio.h>
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#include <soc/romstage.h>
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static const struct mb_cfg baseboard_memcfg = {
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.type = MEM_TYPE_LP5X,
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/*
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* DQ byte map
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*
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* To calculate from schematics, reference
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* ADL_LP5_DqMapCpu2Dram sheet of this spreadsheet:
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* https://cdrdv2.intel.com/v1/dl/getContent/573387
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*/
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.lpx_dq_map = {
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.ddr0 = {
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.dq0 = { 5, 0, 4, 1, 2, 6, 7, 3, },
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.dq1 = { 9, 12, 8, 13, 15, 10, 14, 11, },
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},
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.ddr1 = {
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.dq0 = { 9, 10, 11, 8, 13, 15, 14, 12, },
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.dq1 = { 0, 3, 1, 2, 7, 5, 6, 4, },
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},
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.ddr2 = {
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.dq0 = { 9, 13, 8, 12, 15, 10, 14, 11, },
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.dq1 = { 7, 6, 4, 5, 0, 3, 1, 2, },
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},
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.ddr3 = {
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.dq0 = { 3, 7, 2, 6, 4, 1, 5, 0, },
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.dq1 = { 12, 14, 15, 13, 11, 10, 8, 9, },
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},
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.ddr4 = {
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.dq0 = { 15, 14, 12, 13, 10, 9, 8, 11, },
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.dq1 = { 7, 5, 4, 6, 2, 0, 1, 3, },
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},
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.ddr5 = {
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.dq0 = { 9, 10, 11, 8, 12, 15, 13, 14, },
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.dq1 = { 3, 7, 2, 6, 0, 4, 5, 1, },
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},
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.ddr6 = {
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.dq0 = { 3, 2, 1, 0, 7, 5, 6, 4, },
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.dq1 = { 12, 13, 10, 9, 14, 11, 8, 15, },
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},
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.ddr7 = {
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.dq0 = { 11, 8, 10, 9, 12, 14, 13, 15, },
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.dq1 = { 1, 7, 0, 2, 5, 3, 4, 6, },
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},
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},
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/*
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* DQS CPU<>DRAM map
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*
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* To calculate from schematics, reference
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* MTL_RPL_ADL_LP5_DqsMapCpu2Dram sheet of this spreadsheet:
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* https://cdrdv2.intel.com/v1/dl/getContent/573387
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*/
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.lpx_dqs_map = {
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.ddr0 = { .dqs0 = 0, .dqs1 = 1 },
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.ddr1 = { .dqs0 = 0, .dqs1 = 1 },
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.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
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.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
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.ddr4 = { .dqs0 = 0, .dqs1 = 1 },
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.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
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.ddr6 = { .dqs0 = 0, .dqs1 = 1 },
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.ddr7 = { .dqs0 = 0, .dqs1 = 1 },
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},
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/* Enable Early Command Training */
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.ect = true,
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.UserBd = BOARD_TYPE_MOBILE,
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.lp5x_config = {
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/*
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* CA and CS signals are in descending order.
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*
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* Reference the MTL_RPL_ADL_LP5_CccConfig sheet of
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* this spreadsheet for instructions:
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* https://cdrdv2.intel.com/v1/dl/getContent/573387
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*/
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.ccc_config = 0xff,
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},
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};
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const struct mb_cfg *variant_memory_params(void)
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{
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return &baseboard_memcfg;
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}
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int variant_memory_sku(void)
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{
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/*
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* Memory configuration board straps
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* - MEM_STRAP_0: GPP_E3
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* - MEM_STRAP_1: GPP_E2
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* - MEM_STRAP_2: GPP_E1
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* - MEM_STRAP_3: GPP_E7
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*
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* MEM_STRAP_0 is LSB, and MEM_STRAP_3 is MSB.
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*/
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gpio_t spd_gpios[] = {
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GPP_E3,
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GPP_E2,
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GPP_E1,
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GPP_E7,
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};
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return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
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}
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bool variant_is_half_populated(void)
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{
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/* GPIO_MEM_CH_SEL is GPP_B3 */
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return gpio_get(GPP_B3);
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}
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@ -0,0 +1,8 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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# This is an auto-generated file. Do not edit!!
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# Generated by:
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# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/ghost4adl/memory src/mainboard/google/brya/variants/ghost4adl/memory/mem_parts_used.txt
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SPD_SOURCES =
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SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 0(0b0000) Parts = H9JCNNNBK3MLYR-N6E
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SPD_SOURCES += spd/lp5/set-0/spd-3.hex # ID = 1(0b0001) Parts = H58G56AK6BX069
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@ -0,0 +1,8 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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# This is an auto-generated file. Do not edit!!
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# Generated by:
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# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/ghost4adl/memory src/mainboard/google/brya/variants/ghost4adl/memory/mem_parts_used.txt
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DRAM Part Name ID to assign
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H9JCNNNBK3MLYR-N6E 0 (0000)
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H58G56AK6BX069 1 (0001)
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@ -0,0 +1,13 @@
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# This is a CSV file containing a list of memory parts used by this variant.
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# One part per line with an optional fixed ID in column 2.
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# Only include a fixed ID if it is required for legacy reasons!
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# Generated IDs are dependent on the order of parts in this file,
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# so new parts must always be added at the end of the file!
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#
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# Generate an updated Makefile.inc and dram_id.generated.txt by running the
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# part_id_gen tool from util/spd_tools.
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# See util/spd_tools/README.md for more details and instructions.
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# Part Name
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H9JCNNNBK3MLYR-N6E
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H58G56AK6BX069
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@ -0,0 +1,188 @@
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chip soc/intel/alderlake
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#+-------------------+---------------------------+
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#| Field | Value |
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#+-------------------+---------------------------+
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#| GSPI1 | FPMCU |
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#| I2C0 | Audio |
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#| I2C1 | cr50 TPM. Early init is |
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#| | required to set up a BAR |
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#| | for TPM communication |
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#| I2C2 | Misc (Cam, Display, LED) |
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#| I2C3 | Touchscreen |
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#| I2C4 | NC |
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#| I2C5 | Touchpad |
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#+-------------------+---------------------------+
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register "common_soc_config" = "{
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.i2c[0] = {
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.speed = I2C_SPEED_STANDARD,
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.speed_config[0] = {
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.speed = I2C_SPEED_STANDARD,
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.scl_lcnt = 45,
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.scl_hcnt = 33,
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.sda_hold = 20,
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},
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},
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.i2c[1] = {
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.early_init = 1,
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.speed = I2C_SPEED_STANDARD,
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.rise_time_ns = 600,
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.fall_time_ns = 400,
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.data_hold_time_ns = 50,
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},
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.i2c[2] = {
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.speed = I2C_SPEED_STANDARD,
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.rise_time_ns = 650,
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.fall_time_ns = 400,
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.data_hold_time_ns = 50,
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},
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.i2c[3] = {
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.speed = I2C_SPEED_STANDARD,
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.rise_time_ns = 650,
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.fall_time_ns = 400,
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.data_hold_time_ns = 50,
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},
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.i2c[5] = {
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.speed = I2C_SPEED_STANDARD,
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.rise_time_ns = 650,
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.fall_time_ns = 400,
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.data_hold_time_ns = 50,
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},
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}"
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# I2C Port Config
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register "serial_io_i2c_mode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoPci,
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[PchSerialIoIndexI2C1] = PchSerialIoPci,
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[PchSerialIoIndexI2C2] = PchSerialIoPci,
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[PchSerialIoIndexI2C3] = PchSerialIoPci,
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[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C5] = PchSerialIoPci,
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[PchSerialIoIndexI2C7] = PchSerialIoDisabled,
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}"
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device domain 0 on
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device ref pcie4_0 on
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# Enable CPU PCIE RP 1 using CLK 1
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register "cpu_pcie_rp[CPU_RP(1)]" = "{
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.clk_req = 1,
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.clk_src = 1,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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}"
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end
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device ref tbt_pcie_rp3 on end
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device ref cnvi_wifi on
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chip drivers/wifi/generic
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register "wake" = "GPE0_PME_B0"
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device generic 0 on end
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end
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end
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device ref pcie_rp6 off end
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device ref pcie_rp7 off end
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device ref pcie_rp8 off end
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device ref pcie_rp9 on
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# Enable NVMe on PCIE 9-12 using clk 1
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register "pch_pcie_rp[PCH_RP(9)]" = "{
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.clk_src = 1,
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.clk_req = 0,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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}"
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end
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device ref tcss_dma0 on
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chip drivers/intel/usb4/retimer
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register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
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use tcss_usb3_port1 as dfp[0].typec_port
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device generic 0 on end
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end
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end
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device ref tcss_dma1 on
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chip drivers/intel/usb4/retimer
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register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
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use tcss_usb3_port3 as dfp[0].typec_port
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device generic 0 on end
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end
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end
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device ref i2c1 on
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chip drivers/i2c/tpm
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register "hid" = ""GOOG0005""
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register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
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device i2c 50 on end
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end
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end
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device ref gspi1 on
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chip drivers/spi/acpi
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register "name" = ""CRFP""
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register "hid" = "ACPI_DT_NAMESPACE_HID"
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register "uid" = "1"
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register "compat_string" = ""google,cros-ec-spi""
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register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
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register "wake" = "GPE0_DW2_15"
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device spi 0 on end
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end # FPMCU
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end
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device ref pch_espi on
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chip ec/google/chromeec
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# Replicate Brya, except we have 2 ports instead of 3.
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use conn0 as mux_conn[0]
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use conn1 as mux_conn[1]
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device pnp 0c09.0 on end
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end
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end
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device ref pmc hidden
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chip drivers/intel/pmc_mux
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device generic 0 on
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chip drivers/intel/pmc_mux/conn
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use usb2_port1 as usb2_port
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use tcss_usb3_port3 as usb3_port
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device generic 0 alias conn0 on end
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end
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chip drivers/intel/pmc_mux/conn
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use usb2_port2 as usb2_port
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use tcss_usb3_port2 as usb3_port
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device generic 1 alias conn1 on end
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end
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end
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end
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end
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device ref tcss_xhci on
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chip drivers/usb/acpi
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device ref tcss_root_hub on
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-C Port C0 (DB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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# USB C0 is on RIGHT panel, LEFT side (when user is facing front)
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register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))"
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device ref tcss_usb3_port3 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-C Port C1 (MLB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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# USB C1 is on the RIGHT panel, RIGHT side (when user is facing front)
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register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
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device ref tcss_usb3_port2 on end
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end
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end
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end
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end
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device ref xhci on
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chip drivers/usb/acpi
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device ref xhci_root_hub on
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-C Port C0 (DB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))"
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device ref usb2_port1 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-C Port C1 (MLB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
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device ref usb2_port2 on end
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end
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end
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end
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end
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end
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end
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