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cpu/intel/model_406dx: Remove the notion of CPU sockets 

Change-Id: I5e8fb2e7331d02224a4199c4d05f92c603c57f78
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/31032
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans 2019-01-21 18:12:07 +01:00 committed by Patrick Georgi
parent 7e6946a74c
commit 7701376cca
12 changed files with 12 additions and 32 deletions
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1
src/cpu/intel/Kconfig
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@ -27,7 +27,6 @@ source src/cpu/intel/socket_mPGA478MN/Kconfig
source src/cpu/intel/socket_mPGA604/Kconfig source src/cpu/intel/socket_mPGA604/Kconfig
source src/cpu/intel/socket_441/Kconfig source src/cpu/intel/socket_441/Kconfig
source src/cpu/intel/socket_LGA775/Kconfig source src/cpu/intel/socket_LGA775/Kconfig
source src/cpu/intel/socket_rPGA989/Kconfig
# Architecture specific features # Architecture specific features
source src/cpu/intel/fit/Kconfig source src/cpu/intel/fit/Kconfig
source src/cpu/intel/turbo/Kconfig source src/cpu/intel/turbo/Kconfig

1
src/cpu/intel/Makefile.inc
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@ -11,7 +11,6 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_FCBGA559) += socket_FCBGA559
subdirs-$(CONFIG_CPU_INTEL_SOCKET_MFCPGA478) += socket_mFCPGA478 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MFCPGA478) += socket_mFCPGA478
subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA478MN) += socket_mPGA478MN subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA478MN) += socket_mPGA478MN
subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA604) += socket_mPGA604 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA604) += socket_mPGA604
subdirs-$(CONFIG_CPU_INTEL_SOCKET_RPGA989) += socket_rPGA989
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_NEHALEM) += model_2065x subdirs-$(CONFIG_NORTHBRIDGE_INTEL_NEHALEM) += model_2065x
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += model_206ax subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += model_206ax
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += model_206ax subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += model_206ax

1
src/cpu/intel/fsp_model_406dx/Kconfig
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@ -26,6 +26,7 @@ config CPU_SPECIFIC_OPTIONS
select ARCH_ROMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32
select SMP select SMP
select MMX
select SSE2 select SSE2
select UDELAY_LAPIC select UDELAY_LAPIC
select SUPPORT_CPU_UCODE_IN_CBFS select SUPPORT_CPU_UCODE_IN_CBFS

8
src/cpu/intel/fsp_model_406dx/Makefile.inc
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@ -17,6 +17,14 @@ ramstage-y += model_406dx_init.c
subdirs-y += ../../x86/name subdirs-y += ../../x86/name
subdirs-y += ../common subdirs-y += ../common
subdirs-y += ../../x86/tsc
subdirs-y += ../../x86/mtrr
subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache
subdirs-y += ../../x86/smm
subdirs-y += ../microcode
subdirs-y += ../turbo
ramstage-y += acpi.c ramstage-y += acpi.c
CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_406dx CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_406dx

11
src/cpu/intel/socket_rPGA989/Kconfig
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@ -1,11 +0,0 @@
config CPU_INTEL_SOCKET_RPGA989
bool
if CPU_INTEL_SOCKET_RPGA989
config SOCKET_SPECIFIC_OPTIONS # dummy
def_bool y
select MMX
select SSE
endif

7
src/cpu/intel/socket_rPGA989/Makefile.inc
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@ -1,7 +0,0 @@
subdirs-y += ../../x86/tsc
subdirs-y += ../../x86/mtrr
subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache
subdirs-y += ../../x86/smm
subdirs-y += ../microcode
subdirs-y += ../turbo

1
src/mainboard/adi/rcc-dff/Kconfig
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@ -17,7 +17,6 @@ if BOARD_ADI_RCC_DFF
config BOARD_SPECIFIC_OPTIONS config BOARD_SPECIFIC_OPTIONS
def_bool y def_bool y
select CPU_INTEL_SOCKET_RPGA989
select NORTHBRIDGE_INTEL_FSP_RANGELEY select NORTHBRIDGE_INTEL_FSP_RANGELEY
select SOUTHBRIDGE_INTEL_FSP_RANGELEY select SOUTHBRIDGE_INTEL_FSP_RANGELEY
select BOARD_ROMSIZE_KB_2048 #actual chip is 8MB select BOARD_ROMSIZE_KB_2048 #actual chip is 8MB

4
src/mainboard/adi/rcc-dff/devicetree.cb
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@ -15,10 +15,8 @@
chip northbridge/intel/fsp_rangeley chip northbridge/intel/fsp_rangeley
device cpu_cluster 0 on device cpu_cluster 0 on
chip cpu/intel/socket_rPGA989
device lapic 0 on end
end
chip cpu/intel/fsp_model_406dx chip cpu/intel/fsp_model_406dx
device lapic 0 on end
# Magic APIC ID to locate this chip # Magic APIC ID to locate this chip
device lapic 0xACAC off end device lapic 0xACAC off end

1
src/mainboard/intel/littleplains/Kconfig
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@ -17,7 +17,6 @@ if BOARD_INTEL_LITTLEPLAINS
config BOARD_SPECIFIC_OPTIONS config BOARD_SPECIFIC_OPTIONS
def_bool y def_bool y
select CPU_INTEL_SOCKET_RPGA989
select NORTHBRIDGE_INTEL_FSP_RANGELEY select NORTHBRIDGE_INTEL_FSP_RANGELEY
select SOUTHBRIDGE_INTEL_FSP_RANGELEY select SOUTHBRIDGE_INTEL_FSP_RANGELEY
select BOARD_ROMSIZE_KB_8192 select BOARD_ROMSIZE_KB_8192

4
src/mainboard/intel/littleplains/devicetree.cb
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@ -15,10 +15,8 @@
chip northbridge/intel/fsp_rangeley chip northbridge/intel/fsp_rangeley
device cpu_cluster 0 on device cpu_cluster 0 on
chip cpu/intel/socket_rPGA989
device lapic 0 on end
end
chip cpu/intel/fsp_model_406dx chip cpu/intel/fsp_model_406dx
device lapic 0 on end
# Magic APIC ID to locate this chip # Magic APIC ID to locate this chip
device lapic 0xACAC off end device lapic 0xACAC off end

1
src/mainboard/intel/mohonpeak/Kconfig
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@ -17,7 +17,6 @@ if BOARD_INTEL_MOHONPEAK
config BOARD_SPECIFIC_OPTIONS config BOARD_SPECIFIC_OPTIONS
def_bool y def_bool y
select CPU_INTEL_SOCKET_RPGA989
select NORTHBRIDGE_INTEL_FSP_RANGELEY select NORTHBRIDGE_INTEL_FSP_RANGELEY
select SOUTHBRIDGE_INTEL_FSP_RANGELEY select SOUTHBRIDGE_INTEL_FSP_RANGELEY
select BOARD_ROMSIZE_KB_2048 #actual chip is 8MB select BOARD_ROMSIZE_KB_2048 #actual chip is 8MB

4
src/mainboard/intel/mohonpeak/devicetree.cb
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@ -15,10 +15,8 @@
chip northbridge/intel/fsp_rangeley chip northbridge/intel/fsp_rangeley
device cpu_cluster 0 on device cpu_cluster 0 on
chip cpu/intel/socket_rPGA989
device lapic 0 on end
end
chip cpu/intel/fsp_model_406dx chip cpu/intel/fsp_model_406dx
device lapic 0 on end
# Magic APIC ID to locate this chip # Magic APIC ID to locate this chip
device lapic 0xACAC off end device lapic 0xACAC off end