cpu/intel/model_406dx: Remove the notion of CPU sockets
Change-Id: I5e8fb2e7331d02224a4199c4d05f92c603c57f78 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/31032 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -27,7 +27,6 @@ source src/cpu/intel/socket_mPGA478MN/Kconfig
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source src/cpu/intel/socket_mPGA604/Kconfig
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source src/cpu/intel/socket_441/Kconfig
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source src/cpu/intel/socket_LGA775/Kconfig
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source src/cpu/intel/socket_rPGA989/Kconfig
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# Architecture specific features
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source src/cpu/intel/fit/Kconfig
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source src/cpu/intel/turbo/Kconfig
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@ -11,7 +11,6 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_FCBGA559) += socket_FCBGA559
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subdirs-$(CONFIG_CPU_INTEL_SOCKET_MFCPGA478) += socket_mFCPGA478
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subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA478MN) += socket_mPGA478MN
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subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA604) += socket_mPGA604
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subdirs-$(CONFIG_CPU_INTEL_SOCKET_RPGA989) += socket_rPGA989
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subdirs-$(CONFIG_NORTHBRIDGE_INTEL_NEHALEM) += model_2065x
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subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += model_206ax
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subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += model_206ax
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@ -26,6 +26,7 @@ config CPU_SPECIFIC_OPTIONS
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select ARCH_ROMSTAGE_X86_32
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select ARCH_RAMSTAGE_X86_32
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select SMP
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select MMX
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select SSE2
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select UDELAY_LAPIC
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select SUPPORT_CPU_UCODE_IN_CBFS
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@ -17,6 +17,14 @@ ramstage-y += model_406dx_init.c
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subdirs-y += ../../x86/name
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subdirs-y += ../common
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subdirs-y += ../../x86/tsc
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subdirs-y += ../../x86/mtrr
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subdirs-y += ../../x86/lapic
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subdirs-y += ../../x86/cache
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subdirs-y += ../../x86/smm
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subdirs-y += ../microcode
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subdirs-y += ../turbo
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ramstage-y += acpi.c
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CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_406dx
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@ -1,11 +0,0 @@
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config CPU_INTEL_SOCKET_RPGA989
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bool
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if CPU_INTEL_SOCKET_RPGA989
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config SOCKET_SPECIFIC_OPTIONS # dummy
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def_bool y
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select MMX
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select SSE
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endif
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@ -1,7 +0,0 @@
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subdirs-y += ../../x86/tsc
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subdirs-y += ../../x86/mtrr
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subdirs-y += ../../x86/lapic
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subdirs-y += ../../x86/cache
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subdirs-y += ../../x86/smm
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subdirs-y += ../microcode
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subdirs-y += ../turbo
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@ -17,7 +17,6 @@ if BOARD_ADI_RCC_DFF
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select CPU_INTEL_SOCKET_RPGA989
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select NORTHBRIDGE_INTEL_FSP_RANGELEY
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select SOUTHBRIDGE_INTEL_FSP_RANGELEY
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select BOARD_ROMSIZE_KB_2048 #actual chip is 8MB
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@ -15,10 +15,8 @@
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chip northbridge/intel/fsp_rangeley
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device cpu_cluster 0 on
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chip cpu/intel/socket_rPGA989
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device lapic 0 on end
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end
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chip cpu/intel/fsp_model_406dx
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device lapic 0 on end
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# Magic APIC ID to locate this chip
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device lapic 0xACAC off end
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@ -17,7 +17,6 @@ if BOARD_INTEL_LITTLEPLAINS
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select CPU_INTEL_SOCKET_RPGA989
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select NORTHBRIDGE_INTEL_FSP_RANGELEY
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select SOUTHBRIDGE_INTEL_FSP_RANGELEY
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select BOARD_ROMSIZE_KB_8192
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@ -15,10 +15,8 @@
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chip northbridge/intel/fsp_rangeley
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device cpu_cluster 0 on
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chip cpu/intel/socket_rPGA989
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device lapic 0 on end
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end
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chip cpu/intel/fsp_model_406dx
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device lapic 0 on end
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# Magic APIC ID to locate this chip
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device lapic 0xACAC off end
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@ -17,7 +17,6 @@ if BOARD_INTEL_MOHONPEAK
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select CPU_INTEL_SOCKET_RPGA989
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select NORTHBRIDGE_INTEL_FSP_RANGELEY
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select SOUTHBRIDGE_INTEL_FSP_RANGELEY
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select BOARD_ROMSIZE_KB_2048 #actual chip is 8MB
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@ -15,10 +15,8 @@
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chip northbridge/intel/fsp_rangeley
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device cpu_cluster 0 on
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chip cpu/intel/socket_rPGA989
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device lapic 0 on end
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end
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chip cpu/intel/fsp_model_406dx
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device lapic 0 on end
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# Magic APIC ID to locate this chip
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device lapic 0xACAC off end
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