drivers/crb: Add CRB driver for TPM2 support
Add the Command Response Buffer which is defined in the TPM 2.0 Specs. CRB can be specified with MAINBOARD_HAS_CRB_TPM, even though it is actually SoC/SB specific. Change-Id: I477e45963fe3cdbc02cda9ae99c19142747e4b46 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
This commit is contained in:
Christian Walter
Philipp Deppenwiese
parent
c703814e95
commit
7706a04c60
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@ -0,0 +1,17 @@
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config CRB_TPM
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bool
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help
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CRB TPM driver is enabled!
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config CRB_TPM_BASE_ADDRESS
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hex
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default 0xfed40000
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help
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Base Address of the CRB TPM Command Structure
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config MAINBOARD_HAS_CRB_TPM
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bool
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default n
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select CRB_TPM
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help
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Mainboard has Command Response Buffer support
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@ -0,0 +1,5 @@
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bootblock-$(CONFIG_CRB_TPM) += tis.c tpm.c
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verstage-$(CONFIG_CRB_TPM) += tis.c tpm.c
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romstage-$(CONFIG_CRB_TPM) += tis.c tpm.c
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ramstage-$(CONFIG_CRB_TPM) += tis.c tpm.c
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postcar-$(CONFIG_CRB_TPM) += tis.c tpm.c
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@ -0,0 +1,22 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Google Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef DRIVERS_CRB_CHIP_H
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#define DRIVERS_CRB_CHIP_H
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typedef struct drivers_crb_config {
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} tpm_config_t;
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#endif /* DRIVERS_CRB_CHIP_H */
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@ -0,0 +1,150 @@
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/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/early_variables.h>
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#include <console/console.h>
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#include <security/tpm/tis.h>
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#include <arch/acpigen.h>
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#include <device/device.h>
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#include "tpm.h"
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#include "chip.h"
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static unsigned tpm_is_open CAR_GLOBAL;
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static const struct {
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uint16_t vid;
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uint16_t did;
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const char *device_name;
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} dev_map[] = {
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{0x1ae0, 0x0028, "CR50"},
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{0xa13a, 0x8086, "Intel iTPM"}
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};
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static const char *tis_get_dev_name(struct tpm2_info *info)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(dev_map); i++)
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if ((dev_map[i].vid == info->vendor_id) && (dev_map[i].did == info->device_id))
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return dev_map[i].device_name;
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return "Unknown";
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}
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int tis_open(void)
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{
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if (car_get_var(tpm_is_open)) {
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printk(BIOS_ERR, "%s called twice.\n", __func__);
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return -1;
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}
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return 0;
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}
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int tis_close(void)
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{
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if (car_get_var(tpm_is_open)) {
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/*
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* Do we need to do something here, like waiting for a
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* transaction to stop?
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*/
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car_set_var(tpm_is_open, 0);
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}
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return 0;
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}
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int tis_init(void)
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{
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struct tpm2_info info;
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// Wake TPM up (if necessary)
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if (tpm2_init() != 0)
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return -1;
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tpm2_get_info(&info);
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printk(BIOS_INFO, "Initialized TPM device %s revision %d\n", tis_get_dev_name(&info),
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info.revision);
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return 0;
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}
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int tis_sendrecv(const uint8_t *sendbuf, size_t sbuf_size, uint8_t *recvbuf, size_t *rbuf_len)
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{
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int len = tpm2_process_command(sendbuf, sbuf_size, recvbuf, *rbuf_len);
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if (len == 0)
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return -1;
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*rbuf_len = len;
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return 0;
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}
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#ifdef __RAMSTAGE__
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static void crb_tpm_fill_ssdt(struct device *dev)
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{
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const char *path = acpi_device_path(dev);
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if (!path) {
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path = "\\_SB_.TPM";
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printk(BIOS_DEBUG, "Using default TPM2 ACPI path: '%s'\n", path);
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}
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/* Device */
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acpigen_write_device(path);
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acpigen_write_name_string("_HID", "MSFT0101");
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acpigen_write_name_string("_CID", "MSFT0101");
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acpigen_write_name_integer("_UID", 1);
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acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON);
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/* Resources */
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acpigen_write_name("_CRS");
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acpigen_write_resourcetemplate_header();
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acpigen_write_mem32fixed(1, TPM_CRB_BASE_ADDRESS, 0x5000);
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acpigen_write_resourcetemplate_footer();
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acpigen_pop_len(); /* Device */
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}
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static const char *crb_tpm_acpi_name(const struct device *dev)
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{
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return "TPM";
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}
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static struct device_operations crb_ops = {
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.read_resources = DEVICE_NOOP,
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.set_resources = DEVICE_NOOP,
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#if CONFIG(HAVE_ACPI_TABLES)
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.acpi_name = crb_tpm_acpi_name,
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.acpi_fill_ssdt_generator = crb_tpm_fill_ssdt,
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#endif
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};
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static void enable_dev(struct device *dev)
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{
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dev->ops = &crb_ops;
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}
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struct chip_operations drivers_crb_ops = {CHIP_NAME("CRB TPM").enable_dev = enable_dev};
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#endif /* __RAMSTAGE__ */
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@ -0,0 +1,280 @@
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/*.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*
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* This is a driver for a CRB Interface.
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*
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* The general flow looks like this:
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*
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* TPM starts in IDLE Mode
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*
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* IDLE --> READY --> Command Receiption
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* ^ |
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* | v
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-- Cmd Complete <-- Command Execution
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*/
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#include <timer.h>
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#include <arch/early_variables.h>
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#include <console/console.h>
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#include <arch/mmio.h>
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#include <delay.h>
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#include <string.h>
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#include <endian.h>
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#include <soc/pci_devs.h>
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#include <device/pci_ops.h>
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#include "tpm.h"
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static struct control_area {
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uint32_t request;
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uint32_t status;
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uint32_t cancel;
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uint32_t start;
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uint64_t interrupt_control;
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uint32_t command_size;
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void *command_bfr;
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uint32_t response_size;
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void *response_bfr;
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} control_area;
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static uint8_t cur_loc = 0;
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/* Read Control Area Structure back */
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static void crb_readControlArea(void)
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{
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control_area.request = read32(CRB_REG(cur_loc, CRB_REG_REQUEST));
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control_area.status = read32(CRB_REG(cur_loc, CRB_REG_STATUS));
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control_area.cancel = read32(CRB_REG(cur_loc, CRB_REG_CANCEL));
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control_area.interrupt_control = read64(CRB_REG(cur_loc, CRB_REG_INT_CTRL));
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control_area.command_size = read32(CRB_REG(cur_loc, CRB_REG_CMD_SIZE));
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control_area.command_bfr = (void *)(uint32_t)read64(CRB_REG(cur_loc, CRB_REG_CMD_ADDR));
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control_area.response_size = read32(CRB_REG(cur_loc, CRB_REG_RESP_SIZE));
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control_area.response_bfr =
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(void *)(uint32_t)read64(CRB_REG(cur_loc, CRB_REG_RESP_ADDR));
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}
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/* Wait for Reg to be expected Value */
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static int crb_wait_for_reg32(const void *addr, uint32_t timeoutMs, uint32_t mask,
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uint32_t expectedValue)
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{
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uint32_t regValue;
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struct stopwatch sw;
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// Set up a timer which breaks the loop after timeout
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stopwatch_init_msecs_expire(&sw, timeoutMs);
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while (1) {
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// Now check if the TPM is in IDLE mode
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regValue = read32(addr);
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if ((regValue & mask) == expectedValue)
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return 0;
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if (stopwatch_expired(&sw)) {
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printk(BIOS_ERR,
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"CRB_WAIT: Error - Returning Zero with RegValue: %08x, Mask: %08x, Expected: %08x\n",
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regValue, mask, expectedValue);
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return -1;
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}
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}
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}
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/* CRB PROBE
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*
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* Checks if the CRB Interface is ready
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*/
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static int crb_probe(void)
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{
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uint64_t tpmStatus = read64(CRB_REG(cur_loc, CRB_REG_INTF_ID));
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printk(BIOS_SPEW, "Interface ID Reg. %llx\n", tpmStatus);
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if ((tpmStatus & CRB_INTF_REG_CAP_CRB) == 0) {
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printk(BIOS_DEBUG, "TPM: CRB Interface is not supported.\n");
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return -1;
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}
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if ((tpmStatus & (0xf)) != 1) {
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printk(BIOS_DEBUG,
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"TPM: CRB Interface is not active. System needs reboot in order to active TPM.\n");
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write32(CRB_REG(cur_loc, CRB_REG_INTF_ID), CRB_INTF_REG_INTF_SEL);
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return -1;
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}
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write32(CRB_REG(cur_loc, CRB_REG_INTF_ID), CRB_INTF_REG_INTF_SEL);
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write32(CRB_REG(cur_loc, CRB_REG_INTF_ID), CRB_INTF_REG_INTF_LOCK);
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return 0;
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}
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/*
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* Get active Locality
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*
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* Get the active locality
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*/
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static uint8_t crb_activate_locality(void)
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{
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uint8_t locality = (read8(CRB_REG(0, CRB_REG_LOC_STATE)) >> 2) & 0x07;
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printk(BIOS_SPEW, "Active locality: %i\n", locality);
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int rc = crb_wait_for_reg32(CRB_REG(locality, CRB_REG_LOC_STATE), 750,
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LOC_STATE_LOC_ASSIGN, LOC_STATE_LOC_ASSIGN);
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if (!rc && (locality == 0))
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return locality;
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if (rc)
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write8(CRB_REG(locality, CRB_REG_LOC_CTRL), LOC_CTRL_REQ_ACCESS);
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rc = crb_wait_for_reg32(CRB_REG(locality, CRB_REG_LOC_STATE), 750, LOC_STATE_LOC_ASSIGN,
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LOC_STATE_LOC_ASSIGN);
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if (rc) {
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printk(BIOS_ERR, "TPM: Error - No Locality has been assigned TPM-wise.\n");
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return 0;
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}
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rc = crb_wait_for_reg32(CRB_REG(locality, CRB_REG_LOC_STATE), 1500,
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LOC_STATE_REG_VALID_STS, LOC_STATE_REG_VALID_STS);
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if (rc) {
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printk(BIOS_ERR, "TPM: Error - LOC_STATE Register %u contains errors.\n",
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locality);
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return 0;
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}
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return locality;
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}
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/* Switch Device into a Ready State */
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static int crb_switch_to_ready(void)
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{
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/* Transition into ready state */
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write8(CRB_REG(cur_loc, CRB_REG_REQUEST), 0x1);
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int rc = crb_wait_for_reg32(CRB_REG(cur_loc, CRB_REG_REQUEST), 200,
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CRB_REG_REQUEST_CMD_RDY, 0x0);
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if (rc) {
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printk(BIOS_ERR,
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"TPM: Error - TPM did not transition into ready state in time.\n");
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return -1;
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}
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/* Check TPM_CRB_CTRL_STS[0] to be "0" - no unrecoverable error */
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rc = crb_wait_for_reg32(CRB_REG(cur_loc, CRB_REG_STATUS), 500, CRB_REG_STATUS_ERROR,
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0x0);
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if (rc) {
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printk(BIOS_ERR, "TPM: Fatal Error - Could not recover.\n");
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return -1;
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}
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return 0;
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}
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/*
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* tpm2_init
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*
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* Even though the TPM does not need an initialization we check
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* if the TPM responds and is in IDLE mode, which should be the
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* normal bring up mode.
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*
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*/
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int tpm2_init(void)
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{
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if (crb_probe()) {
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printk(BIOS_ERR, "TPM: Probe failed.\n");
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return -1;
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}
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/* Read back control area structure */
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crb_readControlArea();
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/* Good to go. */
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printk(BIOS_SPEW, "TPM: CRB TPM initialized successfully\n");
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return 0;
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}
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/*
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* tpm2_process_command
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*/
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size_t tpm2_process_command(const void *tpm2_command, size_t command_size, void *tpm2_response,
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size_t max_response)
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{
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int rc;
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if (command_size > control_area.command_size) {
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printk(BIOS_ERR, "TPM: Command size is too big.\n");
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return -1;
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}
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if (control_area.response_size < max_response) {
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printk(BIOS_ERR, "TPM: Response size could be too big.\n");
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return -1;
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}
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cur_loc = crb_activate_locality();
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// Check if CMD bit is cleared.
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rc = crb_wait_for_reg32(CRB_REG(0, CRB_REG_START), 250, CRB_REG_START_START, 0x0);
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if (rc) {
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printk(BIOS_ERR, "TPM: Error - Cmd Bit not cleared.\n");
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return -1;
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}
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if (crb_switch_to_ready())
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return -1;
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// Write to Command Buffer
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memcpy(control_area.command_bfr, tpm2_command, command_size);
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// Write Start Bit
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write8(CRB_REG(cur_loc, CRB_REG_START), 0x1);
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// Poll for Response
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rc = crb_wait_for_reg32(CRB_REG(cur_loc, CRB_REG_START), 3500, CRB_REG_START_START, 0);
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if (rc) {
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printk(BIOS_DEBUG, "TPM: Command Timed out.\n");
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return -1;
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}
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// Check for errors
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rc = crb_wait_for_reg32(CRB_REG(cur_loc, CRB_REG_STATUS), 200, CRB_REG_STATUS_ERROR, 0);
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if (rc) {
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printk(BIOS_DEBUG, "TPM: Command errored.\n");
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return -1;
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}
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// Get Response Length
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uint32_t length = be32_to_cpu(read32(control_area.response_bfr + 2));
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/* Response has to have at least 6 bytes */
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if (length < 6)
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return 1;
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// Copy Response
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memcpy(tpm2_response, control_area.response_bfr, length);
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if (crb_switch_to_ready()) {
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printk(BIOS_DEBUG, "TPM: Can not transition into ready state again.\n");
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return -1;
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}
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return length;
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}
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/*
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* tp2_get_info
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*
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* Returns information about the TPM
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*
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*/
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void tpm2_get_info(struct tpm2_info *tpm2_info)
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{
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uint64_t interfaceReg = read64(CRB_REG(cur_loc, CRB_REG_INTF_ID));
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tpm2_info->vendor_id = (interfaceReg >> 48) & 0xFFFF;
|
||||
tpm2_info->device_id = (interfaceReg >> 32) & 0xFFFF;
|
||||
tpm2_info->revision = (interfaceReg >> 24) & 0xFF;
|
||||
}
|
||||
|
|
@ -0,0 +1,70 @@
|
|||
/*
|
||||
* Copyright 2016 The Chromium OS Authors. All rights reserved.
|
||||
* Use of this source code is governed by a BSD-style license that can be
|
||||
* found in the LICENSE file.
|
||||
*
|
||||
* This is a driver for a Command Response Buffer Interface
|
||||
*/
|
||||
|
||||
/* CRB driver */
|
||||
/* address of locality 0 (CRB) */
|
||||
#define TPM_CRB_BASE_ADDRESS CONFIG_CRB_TPM_BASE_ADDRESS
|
||||
|
||||
#define CRB_REG(LOCTY, REG) \
|
||||
(void *)(CONFIG_CRB_TPM_BASE_ADDRESS + (LOCTY << 12) + REG)
|
||||
|
||||
/* hardware registers */
|
||||
#define CRB_REG_LOC_STATE 0x00
|
||||
#define CRB_REG_LOC_CTRL 0x08
|
||||
#define CRB_REG_LOC_STS 0x0C
|
||||
|
||||
/* LOC_CTRL BIT MASKS */
|
||||
#define LOC_CTRL_REQ_ACCESS 0x01
|
||||
|
||||
/* LOC STATE BIT MASKS */
|
||||
#define LOC_STATE_LOC_ASSIGN 0x02
|
||||
#define LOC_STATE_REG_VALID_STS 0x80
|
||||
|
||||
/* LOC STS BIT MASKS */
|
||||
#define LOC_STS_GRANTED 0x01
|
||||
|
||||
#define CRB_REG_INTF_ID 0x30
|
||||
#define CRB_REG_REQUEST 0x40
|
||||
#define CRB_REG_STATUS 0x44
|
||||
#define CRB_REG_CANCEL 0x48
|
||||
#define CRB_REG_START 0x4C
|
||||
#define CRB_REG_INT_CTRL 0x50
|
||||
#define CRB_REG_CMD_SIZE 0x58
|
||||
#define CRB_REG_CMD_ADDR 0x5C
|
||||
#define CRB_REG_RESP_SIZE 0x64
|
||||
#define CRB_REG_RESP_ADDR 0x68
|
||||
|
||||
/* CRB INTF BIT MASK */
|
||||
#define CRB_INTF_REG_CAP_CRB (1<<14)
|
||||
#define CRB_INTF_REG_INTF_SEL (1<<17)
|
||||
#define CRB_INTF_REG_INTF_LOCK (1<<19)
|
||||
|
||||
|
||||
/*REQUEST Register related */
|
||||
#define CRB_REG_REQUEST_CMD_RDY 0x01
|
||||
#define CRB_REG_REQUEST_GO_IDLE 0x02
|
||||
|
||||
/* STATUS Register related */
|
||||
#define CRB_REG_STATUS_ERROR 0x01
|
||||
#define CRB_REG_STATUS_IDLE 0x02
|
||||
|
||||
/* START Register related */
|
||||
#define CRB_REG_START_START 0x01
|
||||
|
||||
/* TPM Info Struct */
|
||||
struct tpm2_info {
|
||||
uint16_t vendor_id;
|
||||
uint16_t device_id;
|
||||
uint16_t revision;
|
||||
};
|
||||
|
||||
|
||||
int tpm2_init(void);
|
||||
void tpm2_get_info(struct tpm2_info *tpm2_info);
|
||||
size_t tpm2_process_command(const void *tpm2_command, size_t command_size,
|
||||
void *tpm2_response, size_t max_response);
|
||||
|
|
@ -28,7 +28,7 @@ config TPM2
|
|||
default y if MAINBOARD_HAS_TPM2 || USER_TPM2
|
||||
depends on MAINBOARD_HAS_I2C_TPM_GENERIC || MAINBOARD_HAS_LPC_TPM \
|
||||
|| MAINBOARD_HAS_I2C_TPM_ATMEL || MAINBOARD_HAS_I2C_TPM_CR50 \
|
||||
|| MAINBOARD_HAS_SPI_TPM_CR50
|
||||
|| MAINBOARD_HAS_SPI_TPM_CR50 || MAINBOARD_HAS_CRB_TPM
|
||||
|
||||
config MAINBOARD_HAS_TPM1
|
||||
bool
|
||||
|
|
@ -58,7 +58,7 @@ config USER_TPM2
|
|||
bool "2.0"
|
||||
depends on MAINBOARD_HAS_I2C_TPM_GENERIC || MAINBOARD_HAS_LPC_TPM \
|
||||
|| MAINBOARD_HAS_I2C_TPM_ATMEL || MAINBOARD_HAS_I2C_TPM_CR50 \
|
||||
|| MAINBOARD_HAS_SPI_TPM_CR50
|
||||
|| MAINBOARD_HAS_SPI_TPM_CR50 || MAINBOARD_HAS_CRB_TPM
|
||||
help
|
||||
Enable this option to enable TPM 2.0 support in coreboot.
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue