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soc/amd/common/data_fabric_helper: normalize addresses in debug print 

Instead of just printing the register contents, normalize the contents
of the base and limit registers to actual MMIO addresses and then print
those. This will hopefully avoid some confusion caused by the shifted
addresses.

Output on Mandolin before the patch:

=== Data Fabric MMIO configuration registers ===
Addresses are shifted to the right by 16 bits.
idx  control     base    limit
  0       93     fc00     febf
  1       93  1000000 ffffffff
  2       93     d000     f7ff
  3     1093     fed0     fedf
  4       90        0        0
  5       90        0        0
  6       90        0        0
  7       90        0        0

Output on Mandolin after the patch:

=== Data Fabric MMIO configuration registers ===
idx  control             base            limit
  0       93         fc000000         febfffff
  1       93      10000000000     ffffffffffff
  2       93         d0000000         f7ffffff
  3     1093         fed00000         fedfffff
  4       90                0             ffff
  5       90                0             ffff
  6       90                0             ffff
  7       90                0             ffff

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I62eeb88ddac6a7a421fccc8e433523459117976a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
This commit is contained in:
Felix Held 2023-02-02 16:13:05 +01:00
parent 0d34a50a36
commit 77128a8dcd
1 changed files with 14 additions and 7 deletions
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19
src/soc/amd/common/block/data_fabric/data_fabric_helper.c
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@ -47,16 +47,23 @@ void data_fabric_write32(uint8_t function, uint16_t reg, uint8_t instance_id, ui
void data_fabric_print_mmio_conf(void) void data_fabric_print_mmio_conf(void)
{ {
uint32_t control;
uint64_t base, limit;
printk(BIOS_SPEW, printk(BIOS_SPEW,
"=== Data Fabric MMIO configuration registers ===\n" "=== Data Fabric MMIO configuration registers ===\n"
"Addresses are shifted to the right by 16 bits.\n"
"idx control base limit\n"); "idx control base limit\n");
for (unsigned int i = 0; i < NUM_NB_MMIO_REGS; i++) { for (unsigned int i = 0; i < NUM_NB_MMIO_REGS; i++) {
printk(BIOS_SPEW, " %2u %8x %8x %8x\n", control = data_fabric_broadcast_read32(0, NB_MMIO_CONTROL(i));
i, /* Base and limit address registers don't contain the lower address bits, but
data_fabric_broadcast_read32(0, NB_MMIO_CONTROL(i)), are shifted by D18F0_MMIO_SHIFT bits */
data_fabric_broadcast_read32(0, NB_MMIO_BASE(i)), base = (uint64_t)data_fabric_broadcast_read32(0, NB_MMIO_BASE(i))
data_fabric_broadcast_read32(0, NB_MMIO_LIMIT(i))); << D18F0_MMIO_SHIFT;
limit = (uint64_t)data_fabric_broadcast_read32(0, NB_MMIO_LIMIT(i))
<< D18F0_MMIO_SHIFT;
/* Lower D18F0_MMIO_SHIFT address limit bits are all 1 */
limit += (1 << D18F0_MMIO_SHIFT) - 1;
printk(BIOS_SPEW, " %2u %8x %16llx %16llx\n",
i, control, base, limit);
} }
} }