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sb/amd/sr5650: Correctly locate CPU MMCONFIG resource 

The code committed in GIT hash
 * 1eaaa0 southbridge/amd/sr5650:Add MCFG ACPI table support
did not correctly locate the CPU MMCONFIG resource, leading to failures
with operating systems and firmware (e.g. SeaBIOS) when the PCI
extended configuration space option was activated.

Due to the southbridge routing not being set up, MMCONFIG accesses were
targetting DRAM and therefore the PCI devices were not being configured.
The failure normally manifests as a system hang immediately after PCI
configuration starts.

Search for the CPU MMCONFIG resource on all domains below the root
device.

Change-Id: I0df2f825fef2de46563db87af78d0609ab3d8c5a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12821
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Timothy Pearson 2016-01-01 23:30:42 -06:00 committed by Martin Roth
parent ada36d4cff
commit 77133afe31
1 changed files with 4 additions and 4 deletions
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8
src/southbridge/amd/sr5650/sr5650.c
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@ -35,13 +35,13 @@ extern void set_pcie_dereset(void);
extern void set_pcie_reset(void); extern void set_pcie_reset(void);
struct resource * sr5650_retrieve_cpu_mmio_resource() { struct resource * sr5650_retrieve_cpu_mmio_resource() {
device_t cpu; device_t domain;
struct resource *res; struct resource *res;
for (cpu = all_devices; cpu; cpu = cpu->next) { for (domain = all_devices; domain; domain = domain->next) {
if (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER) if (domain->bus->dev->path.type != DEVICE_PATH_DOMAIN)
continue; continue;
res = probe_resource(cpu->bus->dev, 0xc0010058); res = probe_resource(domain->bus->dev, 0xc0010058);
if (res) if (res)
return res; return res;
} }