From 7719d50352272e27528f99e60df1c861300e14a9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= Date: Sun, 15 Apr 2018 20:33:50 +0200 Subject: [PATCH] Documentation/Intel: Adjust heading levels MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Adjust the headings so that there is only one h1 tag per file. Change-Id: I53f9ee47957fcde521b64c0123dac10f051c681c Signed-off-by: Jonathan Neuschäfer Reviewed-on: https://review.coreboot.org/25684 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Martin Roth --- Documentation/Intel/Board/board.html | 10 ++--- Documentation/Intel/Board/galileo.html | 8 ++-- Documentation/Intel/SoC/quark.html | 14 +++---- Documentation/Intel/SoC/soc.html | 52 +++++++++++++------------- Documentation/Intel/fsp1_1.html | 12 +++--- Documentation/Intel/index.html | 20 +++++----- Documentation/Intel/vboot.html | 26 ++++++------- 7 files changed, 72 insertions(+), 70 deletions(-) diff --git a/Documentation/Intel/Board/board.html b/Documentation/Intel/Board/board.html index d09805bddd..4ba51df401 100644 --- a/Documentation/Intel/Board/board.html +++ b/Documentation/Intel/Board/board.html @@ -22,7 +22,7 @@
-

Required Files

+

Required Files

Create the board directory as src/mainboard/<Vendor>/<Board>.

@@ -80,7 +80,7 @@
-

Enable Serial Output

+

Enable Serial Output

Use the following steps to enable serial output:

@@ -103,7 +103,7 @@
-

Memory Timing Data

+

Memory Timing Data

Memory timing data is located in the flash. This data is in the format of serial presence detect @@ -183,7 +183,7 @@

-

Disable PCI Devices

+

Disable PCI Devices

Ramstage's BS_DEV_ENUMERATE state displays the PCI vendor and device IDs for all of the devices in the system. Edit the devicetree.cb file: @@ -209,7 +209,7 @@

-

ACPI Tables

+

ACPI Tables

  1. Edit Kconfig
      diff --git a/Documentation/Intel/Board/galileo.html b/Documentation/Intel/Board/galileo.html index cdc8fda85f..cd0a28ac35 100644 --- a/Documentation/Intel/Board/galileo.html +++ b/Documentation/Intel/Board/galileo.html @@ -26,7 +26,7 @@
      -

      Galileo Board Documentation

      +

      Galileo Board Documentation

    -

    Building QuarkFspPkg

    +

    Building QuarkFspPkg

    There are two versions of FSP: FSP 1.1 and FSP 2.0. There are also two different implementations of FSP, one using subroutines without SEC and @@ -157,7 +157,7 @@ Build commands shown building debug FSP:

    2. -

    Copying FSP files into coreboot Source Tree

    +

    Copying FSP files into coreboot Source Tree

    There are some helper scripts to copy the FSP output into the coreboot source tree. The parameters to these scripts are: @@ -182,7 +182,7 @@ Script files:

    -

    Quark™ EDK2 BIOS

    +

    Quark™ EDK2 BIOS

    Build Instructions:

    diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html index 147b0a1a8e..d91166fd2c 100644 --- a/Documentation/Intel/SoC/soc.html +++ b/Documentation/Intel/SoC/soc.html @@ -39,7 +39,7 @@
    -

    Required Files

    +

    Required Files

    Create the directory as src/soc/<Vendor>/<Chip Family>.

    @@ -69,13 +69,13 @@
    -

    Start Booting

    +

    Start Booting

    Some SoC parts require additional firmware components in the flash. This section describes how to add those pieces.

    -

    Intel Firmware Descriptor

    +

    Intel Firmware Descriptor

    The Intel Firmware Descriptor (IFD) is located at the base of the flash part. The following command overwrites the base of the flash image with the Intel @@ -84,7 +84,7 @@ 

    dd if=descriptor.bin of=build/coreboot.rom conv=notrunc >/dev/null 2>&1
    -

    Management Engine Binary

    +

    Management Engine Binary

    Some SoC parts contain and require that the Management Engine (ME) be running before it is possible to bring the x86 processor out of reset. A binary file @@ -96,14 +96,14 @@ mv build/coreboot.rom.new build/coreboot.rom -

    Early Debug

    +

    Early Debug

    Early debugging between the reset vector and the time the serial port is enabled is most easily done by writing values to port 0x80.

    -

    Success

    +

    Success

    When the reset vector is successfully invoked, port 0x80 will output the following value:

    @@ -118,7 +118,7 @@ mv build/coreboot.rom.new build/coreboot.rom
    -

    Bootblock

    +

    Bootblock

    Implement the bootblock using the following steps:

    @@ -213,7 +213,7 @@ mv build/coreboot.rom.new build/coreboot.rom
    -

    TempRamInit

    +

    TempRamInit

    Enable the call to TempRamInit in two stages:

    @@ -223,7 +223,7 @@ mv build/coreboot.rom.new build/coreboot.rom
-

Find FSP Binary

+

Find FSP Binary

Use the following steps to locate the FSP binary:

@@ -267,7 +267,7 @@ Use the following steps to locate the FSP binary: -

Calling TempRamInit

+

Calling TempRamInit

Use the following steps to debug the call to TempRamInit:

@@ -301,9 +301,9 @@ Use the following steps to debug the call to TempRamInit:
-

Romstage

+

Romstage

-

Serial Output

+

Serial Output

The following steps add the serial output support for romstage:

@@ -339,7 +339,7 @@ Use the following steps to debug the call to TempRamInit: -

Determine Previous Sleep State

+

Determine Previous Sleep State

The following steps implement the code to get the previous sleep state:

@@ -362,7 +362,7 @@ Use the following steps to debug the call to TempRamInit: -

MemoryInit Support

+

MemoryInit Support

The following steps implement the code to support the FSP MemoryInit call:

@@ -390,7 +390,7 @@ Use the following steps to debug the call to TempRamInit: -

Disable Shadow ROM

+

Disable Shadow ROM

A shadow of the SPI flash part is mapped from 0x000e0000 to 0x000fffff. This shadow needs to be disabled to allow RAM to properly respond to @@ -402,9 +402,9 @@ Use the following steps to debug the call to TempRamInit:

-

Ramstage

+

Ramstage

-

Start Device Tree Processing

+

Start Device Tree Processing

The src/mainboard/<Vendor>/<Board>/devicetree.cb file drives the execution during ramstage. This file is processed by the util/sconfig utility @@ -417,7 +417,7 @@ Use the following steps to debug the call to TempRamInit: state of the state machine.

-

Chip Operations

+

Chip Operations

Kick-starting the ramstage state machine requires creating the operation table for the chip listed in devicetree.cb: @@ -437,7 +437,7 @@ Use the following steps to debug the call to TempRamInit:

  • Edit src/soc/<SoC Vendor>/<SoC Family>/Makefile.inc and add chip.c to ramstage
    • -

    Domain Operations

    +

    Domain Operations

    coreboot uses the domain operation table to initiate operations on all of the devices in the domain. By default coreboot enables all PCI devices which it @@ -482,7 +482,7 @@ Use the following steps to debug the call to TempRamInit: -

    PCI Device Drivers

    +

    PCI Device Drivers

    PCI device drivers consist of a ".c" file which contains a "pci_driver" data structure at the end of the file with the attribute tag "__pci_driver". This @@ -509,7 +509,7 @@ Use the following steps to debug the call to TempRamInit: -

    Subsystem IDs

    +

    Subsystem IDs

    PCI subsystem IDs are assigned during the BS_DEV_ENABLE state. The device driver may use the common mechanism to assign subsystem IDs by adding @@ -534,7 +534,7 @@ Use the following steps to debug the call to TempRamInit: -

    Set up the Memory Map

    +

    Set up the Memory Map

    The memory map is built by the various PCI device drivers during the BS_DEV_RESOURCES state of ramstage. The northcluster driver will typically @@ -571,12 +571,12 @@ Use the following steps to debug the call to TempRamInit:

    -

    ACPI Tables

    +

    ACPI Tables

    One of the payloads that needs ACPI tables is the EDK2 CorebootPayloadPkg.

    -

    FADT

    +

    FADT

    The EDK2 module CorebootModulePkg/Library/CbParseLib/CbParseLib.c @@ -679,7 +679,7 @@ Use the following steps to debug the call to TempRamInit:

    -

    Legacy Hardware

    +

    Legacy Hardware

    One of the payloads that needs legacy hardare is the EDK2 CorebootPayloadPkg.

    @@ -731,4 +731,4 @@ Use the following steps to debug the call to TempRamInit:

    Modified: 4 March 2016

    - \ No newline at end of file + diff --git a/Documentation/Intel/fsp1_1.html b/Documentation/Intel/fsp1_1.html index 1e1e88fcb3..94cb6bf8be 100644 --- a/Documentation/Intel/fsp1_1.html +++ b/Documentation/Intel/fsp1_1.html @@ -5,7 +5,9 @@ -

    x86 FSP 1.1 Integration

    +

    FSP 1.1

    + +

    x86 FSP 1.1 Integration

    Firmware Support Package (FSP) integration requires System-on-a-Chip (SoC) and board support. The combined steps are listed @@ -26,8 +28,8 @@

    -

    Required Files

    -

    coreboot Required Files

    +

    Required Files

    +

    coreboot Required Files

    1. Create the following directories if they do not already exist:
        @@ -47,7 +49,7 @@
        -

        Add the FSP Binary File to coreboot File System

        +

        Add the FSP Binary File to coreboot File System

        Add the FSP binary to the coreboot flash image using the following command:

        @@ -59,7 +61,7 @@
        -

        Enable coreboot/FSP Debugging

        +

        Enable coreboot/FSP Debugging

        Set the following Kconfig values:

        diff --git a/Documentation/Intel/index.html b/Documentation/Intel/index.html index b2e826d590..b4daa960a9 100644 --- a/Documentation/Intel/index.html +++ b/Documentation/Intel/index.html @@ -5,15 +5,15 @@ -

        Intel® x86 Boards

        +

        Intel® x86

        + +

        Intel® x86 Boards

        - - -

        Intel® x86 SoCs

        +

        Intel® x86 SoCs

        @@ -21,7 +21,7 @@
        -

        x86 coreboot Development

        +

        x86 coreboot Development

        • Get the coreboot source
        • Overall development
          • @@ -35,7 +35,7 @@
          -

          Payload Development

          +

          Payload Development

          • CorebootPayloadPkg
              @@ -50,13 +50,13 @@
              -

              Documentation

              +

              Documentation

              -

              EDK-II Documentation

              +

              EDK-II Documentation

              -

              FSP Documentation

              +

              FSP Documentation

              • Intel® Firmware Support Package External Architecture Specification V2.0
              • Intel® Firmware Support Package External Architecture Specification V1.1
              • Intel® Firmware Support Package External Architecture Specification V1.0
              -

              Feature Documentation

              +

              Feature Documentation

              diff --git a/Documentation/Intel/vboot.html b/Documentation/Intel/vboot.html index 3a92989317..ca49ac2e2d 100644 --- a/Documentation/Intel/vboot.html +++ b/Documentation/Intel/vboot.html @@ -24,7 +24,7 @@ Google's vboot verifies the firmware and places measurements within the TPM.
              -

              Root of Trust

              +

              Root of Trust

              When using vboot, the root-of-trust is basically the read-only portion of the SPI flash. The following items factor into the trust equation: @@ -57,7 +57,7 @@ flash maintains the manufactured state during the system's lifetime.

              -

              Firmware Layout

              +

              Firmware Layout

              Several sections are added to the firmware layout to support vboot:

              @@ -71,7 +71,7 @@ Several sections are added to the firmware layout to support vboot: The following sections describe the various portions of the flash layout.

              -

              Read-Only Section

              +

              Read-Only Section

              The read-only section contains a coreboot file system (CBFS) that contains all of the boot firmware necessary to perform recovery for the system. This @@ -87,14 +87,14 @@ size and must cover the entire read-only section which consists of:

            • coreboot file system containing read-only recovery firmware
              • -

              Google Binary Blob (GBB) Area

              +

              Google Binary Blob (GBB) Area

              The GBB area is part of the read-only section. This area contains a 4096 or 8192 bit public root RSA key that is used to verify the VBLOCK area to obtain the firmware signing key.

              -

              Recovery Firmware

              +

              Recovery Firmware

              The recovery firmware is contained within a coreboot file system and consists of: @@ -129,7 +129,7 @@ SPI flash device to boot the system.

              -

              Read/Write Section

              +

              Read/Write Section

              The read/write sections contain an area which contains the firmware signing @@ -158,7 +158,7 @@ These files also produce the tables which get passed to the operating system.

              -

              Firmware Updates

              +

              Firmware Updates

              The read/write sections exist in one of three states:

              @@ -208,7 +208,7 @@ gets corrupted.

              -

              Build Flags

              +

              Build Flags

              The following Kconfig values need to be selected to enable vboot:

              @@ -255,7 +255,7 @@ systems in FW_MAIN_A and FW_MAIN_B.

              -

              Signing the coreboot Image

              +

              Signing the coreboot Image

              The following command script is an example of how to sign the coreboot image file. This script is used on the Intel Galileo board and creates the GBB area and @@ -341,7 +341,7 @@ gbb_utility \

              -

              Boot Flow

              +

              Boot Flow

              The reset vector exist in the read-only area and points to the bootblock entry point. The only copy of the bootblock exists in the read-only area of the SPI @@ -367,7 +367,7 @@ not valid vboot falls back to the read-only area to boot into system recovery.

              -

              Chromebook Special Features

              +

              Chromebook Special Features

              Google's Chromebooks have some special features:

              @@ -376,7 +376,7 @@ Google's Chromebooks have some special features:
            • Write-protect screw
              • -

              Developer Mode

              +

              Developer Mode

              Developer mode allows the user to use coreboot to boot another operating system. This may be a another (beta) version of Chrome OS, or another flavor of @@ -386,7 +386,7 @@ This prevents someone from entering developer mode to subvert the system security to access files on the local system or cloud.

              -

              Write Protect Screw

              +

              Write Protect Screw

              Chromebooks have a write-protect screw which provides the ground to the write-protect pin of the SPI flash. Google specifically did this to allow

              Feature/SpecificationLinux View/TestEDK-II View/Test