From 77298c6820a0f4424a41d9f740f379f88f51e406 Mon Sep 17 00:00:00 2001
From: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Date: Wed, 10 Mar 2021 21:09:37 +0530
Subject: [PATCH] soc/intel/alderlake: add processor power limits control
 support

Add processor power limits control support to configure values for
alderlake soc based platforms.

BRANCH=None
BUG=None
TEST=Build and test on alderlake rvp board

Change-Id: I9dc37c7a43e6bd6f1ff5e8a97e22a0c7ac421802
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
---
 src/soc/intel/alderlake/Kconfig       |  1 +
 src/soc/intel/alderlake/chip.h        |  4 ++++
 src/soc/intel/alderlake/systemagent.c | 13 ++++++++++++-
 3 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 522fe53560..37e6a946f0 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -59,6 +59,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_BLOCK_HDA
 	select SOC_INTEL_COMMON_BLOCK_IPU
 	select SOC_INTEL_COMMON_BLOCK_MEMINIT
+	select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
 	select SOC_INTEL_COMMON_BLOCK_SA
 	select SOC_INTEL_COMMON_BLOCK_SMM
 	select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index e1ac015e96..3bee09d01f 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -7,6 +7,7 @@
 #include <intelblocks/cfg.h>
 #include <intelblocks/gpio.h>
 #include <intelblocks/gspi.h>
+#include <intelblocks/power_limit.h>
 #include <intelblocks/pcie_rp.h>
 #include <soc/gpe.h>
 #include <soc/pci_devs.h>
@@ -24,6 +25,9 @@ struct soc_intel_alderlake_config {
 	/* Common struct containing soc config data required by common code */
 	struct soc_intel_common_config common_soc_config;
 
+	/* Common struct containing power limits configuration information */
+	struct soc_power_limits_config power_limits_config;
+
 	/* Gpio group routed to each dword of the GPE0 block. Values are
 	 * of the form PMC_GPP_[A:U] or GPD. */
 	uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */
diff --git a/src/soc/intel/alderlake/systemagent.c b/src/soc/intel/alderlake/systemagent.c
index 35043c61ac..eb1defc87a 100644
--- a/src/soc/intel/alderlake/systemagent.c
+++ b/src/soc/intel/alderlake/systemagent.c
@@ -8,8 +8,11 @@
 
 #include <device/device.h>
 #include <device/pci.h>
+#include <delay.h>
+#include <intelblocks/power_limit.h>
 #include <intelblocks/systemagent.h>
 #include <soc/iomap.h>
+#include <soc/soc_chip.h>
 #include <soc/systemagent.h>
 
 /*
@@ -48,12 +51,20 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index)
  */
 void soc_systemagent_init(struct device *dev)
 {
+	struct soc_power_limits_config *soc_config;
+	config_t *config;
+
 	/* Enable Power Aware Interrupt Routing */
 	enable_power_aware_intr();
 
 	/* Enable BIOS Reset CPL */
 	enable_bios_reset_cpl();
-	/* TODO: Add set_power_limits() */
+
+	/* Configure turbo power limits 1ms after reset complete bit */
+	mdelay(1);
+	config = config_of_soc();
+	soc_config = &config->power_limits_config;
+	set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config);
 }
 
 uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz)