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soc/intel/tigerlake: Generate PMC ACPI device at runtime 

In an attempt to help reduce the amount of static ASL files that are
littered throughout the codebase, pmc.asl was converted to runtime SSDT
generation instead. If future SoCs reuse the same PMC, then this
function can be moved to soc/intel/common/block/pmc for example.

TEST=Verified the following was in the decompiled SSDT:
    Scope (\_SB.PCI0)
    {
        Device (PMC)
        {
            Name (_HID, "INTC1026")  // _HID: Hardware ID
            Name (_DDN, "Intel(R) Tiger Lake IPC Controller")
            Name (_CRS, ResourceTemplate ()
            {
                Memory32Fixed (ReadWrite,
                    0xFE000000,         // Address Base
                    0x00010000,         // Address Length
                    )
            })
        }
    }

Also the following found in linux's /var/log/messages:
"acpi INTC1026:00: GPIO: looking up 0 in _CRS", indicating the PMC
ACPI device was found and its _CRS was locatable.

Change-Id: I665c873d8a80bd503acc4a9f0241c7a6ea425e16
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Tim Wawrzynczak 2020-05-14 16:21:09 -06:00 committed by Duncan Laurie
parent 0013623b7c
commit 7729b29a58
3 changed files with 30 additions and 29 deletions
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26
src/soc/intel/tigerlake/acpi/pmc.asl
View File

@ -1,26 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/iomap.h>
Scope (\_SB.PCI0) {
Device (PMC)
{
Name (_HID, "INTC1026")
Name (_DDN, "Intel(R) Tiger Lake IPC Controller")
/*
* PCH preserved 32 MB MMIO range from 0xFC800000 to 0xFE7FFFFF.
* 64KB (0xFE000000 - 0xFE00FFFF) for PMC MBAR.
*/
Name (_CRS, ResourceTemplate () {
Memory32Fixed (ReadWrite, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE)
})
/* The OS mux driver will be bound to this device node. */
Device (MUX)
{
Name (_HID, "INTC105C")
Name (_DDN, "Intel(R) Tiger Lake North Mux-Agent")
}
}
}

3
src/soc/intel/tigerlake/acpi/southbridge.asl
View File

@ -26,9 +26,6 @@
/* PCIE Ports */
#include "pcie.asl"
/* pmc 0:1f.2 */
#include "pmc.asl"
/* Serial IO */
#include "serialio.asl"

30
src/soc/intel/tigerlake/pmc.c
View File

@ -6,6 +6,7 @@
* Chapter number: 4
*/
#include <acpi/acpigen.h>
#include <bootstate.h>
#include <console/console.h>
#include <device/mmio.h>
@ -17,6 +18,8 @@
#include <soc/pm.h>
#include <soc/soc_chip.h>
#define PMC_HID "INTC1026"
enum pch_pmc_xtal pmc_get_xtal_freq(void)
{
uint8_t *const pmcbase = pmc_mmio_regs();
@ -96,9 +99,36 @@ static void soc_pmc_read_resources(struct device *dev)
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
static void soc_pmc_fill_ssdt(const struct device *dev)
{
acpigen_write_scope(acpi_device_scope(dev));
acpigen_write_device(acpi_device_name(dev));
acpigen_write_name_string("_HID", PMC_HID);
acpigen_write_name_string("_DDN", "Intel(R) Tiger Lake IPC Controller");
/*
* Part of the PCH's reserved 32 MB MMIO range (0xFC800000 - 0xFE7FFFFF).
* The PMC gets 0xFE000000 - 0xFE00FFFF.
*/
acpigen_write_name("_CRS");
acpigen_write_resourcetemplate_header();
acpigen_write_mem32fixed(1, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE);
acpigen_write_resourcetemplate_footer();
acpigen_pop_len(); /* PMC Device */
acpigen_pop_len(); /* Scope */
printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), dev->chip_ops->name,
dev_path(dev));
}
struct device_operations pmc_ops = {
.read_resources = soc_pmc_read_resources,
.set_resources = noop_set_resources,
.enable = pmc_init,
#if CONFIG(HAVE_ACPI_TABLES)
.acpi_fill_ssdt = soc_pmc_fill_ssdt,
#endif
.scan_bus = scan_static_bus,
};