soc/intel/cmn/lpc: Add APIs to enable/disable LPC write protect (WP)
This patch implements two APIs to perform LPC/eSPI write protect enable/ disable operation using PCI configuration space register 0xDC (BIOS Controller). BUG=b:211954778 TEST=Able to build and boot google/redrix to OS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8ce831218025a1d682ea2ad6be76901b0345b362 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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@ -99,4 +99,8 @@ unsigned long southbridge_write_acpi_tables(const struct device *device,
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unsigned long current,
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struct acpi_rsdp *rsdp);
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const uint8_t *lpc_get_pic_pirq_routing(size_t *num);
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/* Enable LPC Write Protect. */
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void lpc_enable_wp(void);
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/* Disable LPC Write Protect. */
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void lpc_disable_wp(void);
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#endif /* _SOC_COMMON_BLOCK_LPC_LIB_H_ */
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@ -26,6 +26,7 @@
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#define LPC_BIOS_CNTL 0xdc
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#define LPC_BC_BILD (1 << 7) /* BILD */
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#define LPC_BC_LE (1 << 1) /* LE */
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#define LPC_BC_WPD (1 << 0) /* WPD */
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#define LPC_BC_EISS (1 << 5) /* EISS */
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#define LPC_PCCTL 0xE0 /* PCI Clock Control */
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#define LPC_PCCTL_CLKRUN_EN (1 << 0)
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@ -195,6 +195,31 @@ void lpc_set_eiss(void)
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lpc_set_bios_control_reg(LPC_BC_EISS);
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}
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static void lpc_configure_write_protect(bool status)
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{
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const pci_devfn_t dev = PCH_DEV_LPC;
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uint8_t bios_cntl;
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bios_cntl = pci_read_config8(dev, LPC_BIOS_CNTL);
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if (status)
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bios_cntl &= ~LPC_BC_WPD;
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else
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bios_cntl |= LPC_BC_WPD;
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pci_write_config8(dev, LPC_BIOS_CNTL, bios_cntl);
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}
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/* Enable LPC Write Protect. */
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void lpc_enable_wp(void)
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{
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lpc_configure_write_protect(true);
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}
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/* Disable LPC Write Protect. */
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void lpc_disable_wp(void)
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{
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lpc_configure_write_protect(false);
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}
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/*
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* Set LPC Serial IRQ mode.
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*/
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