intel CAR: Fix DCACHE_RAM_BASE for old sockets

When using fixed MTRRs for CAR setup, CONFIG_DCACHE_RAM_BASE is ignored
and was not correctly set on affected sockets and boards. It was still
referenced in romstage linker script. This was discovered by clang builds
failing for cases where DCACHE_RAM_BASE = 0, while gcc builds passed.

The actual DCACHE_RAM_BASE programming is base = 0xd0000 - size, as taken
from intel/cpu/cache_as_ram.inc.

Change-Id: Ied5ab2e9683f12990f1aad48ee15eaf91133121c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7887
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

src/cpu/intel/slot_1/Kconfig

@@ -30,6 +30,10 @@ config SLOT_SPECIFIC_OPTIONS # dummy
 	select CPU_INTEL_MODEL_6BX
 	select CPU_INTEL_MODEL_6XX
 
+config DCACHE_RAM_BASE
+	hex
+	default 0xcf000
+
 config DCACHE_RAM_SIZE
 	hex
 	default 0x01000

src/cpu/intel/socket_FC_PGA370/Kconfig

@@ -24,7 +24,14 @@ config CPU_INTEL_SOCKET_FC_PGA370
 	select MMX
 	select SSE
 
+if CPU_INTEL_SOCKET_FC_PGA370
+
+config DCACHE_RAM_BASE
+	hex
+	default 0xc8000
+
 config DCACHE_RAM_SIZE
 	hex
-	default 0x8000
+	default 0x08000
-	depends on CPU_INTEL_SOCKET_FC_PGA370
+
+endif

src/cpu/intel/socket_PGA370/Kconfig

@@ -30,6 +30,10 @@ config SSE2
 	bool
 	default n
 
+config DCACHE_RAM_BASE
+	hex
+	default 0xcf000
+
 config DCACHE_RAM_SIZE
 	hex
 	default 0x01000

src/cpu/intel/socket_mFCBGA479/Kconfig

@@ -3,3 +3,15 @@ config CPU_INTEL_SOCKET_MFCBGA479
 	select CPU_INTEL_MODEL_6BX
 	select MMX
 	select SSE
+
+if CPU_INTEL_SOCKET_MFCBGA479
+
+config DCACHE_RAM_BASE
+	hex
+	default 0xc8000
+
+config DCACHE_RAM_SIZE
+	hex
+	default 0x08000
+
+endif

src/cpu/intel/socket_mPGA479M/Kconfig

@@ -6,3 +6,15 @@ config CPU_INTEL_SOCKET_MPGA479M
 	select CPU_INTEL_MODEL_F2X
 	select MMX
 	select SSE
+
+if CPU_INTEL_SOCKET_MPGA479M
+
+config DCACHE_RAM_BASE
+	hex
+	default 0xc8000
+
+config DCACHE_RAM_SIZE
+	hex
+	default 0x08000
+
+endif

src/mainboard/digitallogic/adl855pc/Kconfig

@@ -18,14 +18,6 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "smartModule855"
 
-config DCACHE_RAM_BASE
-	hex
-	default 0xffdf8000
-
-config DCACHE_RAM_SIZE
-	hex
-	default 0x8000
-
 config IRQ_SLOT_COUNT
 	int
 	default 5

src/mainboard/intel/mtarvon/Kconfig

@@ -23,14 +23,6 @@ config IRQ_SLOT_COUNT
 	int
 	default 1
 
-config DCACHE_RAM_BASE
-	hex
-	default 0xffdf8000
-
-config DCACHE_RAM_SIZE
-	hex
-	default 0x8000
-
 config MAX_CPUS
 	int
 	default 4

src/mainboard/lanner/em8510/Kconfig

@@ -18,14 +18,6 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "EM-8510"
 
-config DCACHE_RAM_BASE
-	hex
-	default 0xffdf8000
-
-config DCACHE_RAM_SIZE
-	hex
-	default 0x8000
-
 config IRQ_SLOT_COUNT
 	int
 	default 10

src/mainboard/rca/rm4100/Kconfig

@@ -18,14 +18,6 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "RM4100"
 
-config DCACHE_RAM_BASE
-	hex
-	default 0xffdf8000
-
-config DCACHE_RAM_SIZE
-	hex
-	default 0x8000
-
 config IRQ_SLOT_COUNT
 	int
 	default 7

src/mainboard/thomson/ip1000/Kconfig

@@ -19,14 +19,6 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "IP1000"
 
-config DCACHE_RAM_BASE
-	hex
-	default 0xffdf8000
-
-config DCACHE_RAM_SIZE
-	hex
-	default 0x8000
-
 config IRQ_SLOT_COUNT
 	int
 	default 7