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mb/*/mptable.c: Use smp_write_pci_intsrc() 

Split parameter '(devfn << 2) | intx' to 'devfn, intx'.

Formatted with 'spatch --max-width 96'

Change-Id: I17a6b3919b6e55aaa7ca2873ca713b36ebe7d3a6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55285
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2021-06-07 22:18:35 +03:00
parent 860cff96dc
commit 7742aedb0f
7 changed files with 90 additions and 106 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/asus/p2b/variants/p2b-d/mptable.c
View File

@ -23,7 +23,7 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0);
/* I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x13, ioapic_id, 0x13); /* UHCI */
smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x04, 3, ioapic_id, 0x13); /* UHCI */
/* Local Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */
mptable_lintsrc(mc, isa_bus);

4
src/mainboard/asus/p2b/variants/p2b-ds/mptable.c
View File

@ -23,8 +23,8 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0);
/* I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x13, ioapic_id, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x18, ioapic_id, 0x13);
smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x04, 3, ioapic_id, 0x13);
smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x06, 0, ioapic_id, 0x13);
/* Local Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */
mptable_lintsrc(mc, 0x1);

28
src/mainboard/getac/p470/mptable.c
View File

@ -24,28 +24,28 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0);
/* Builtin devices on Bus 0 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x8, ioapic_id, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x7d, ioapic_id, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x74, ioapic_id, 0x17);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x75, ioapic_id, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x76, ioapic_id, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x77, ioapic_id, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x6c, ioapic_id, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x70, ioapic_id, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x71, ioapic_id, 0x11);
smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x02, 0, ioapic_id, 0x10);
smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1f, 1, ioapic_id, 0x13);
smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1d, 0, ioapic_id, 0x17);
smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1d, 1, ioapic_id, 0x13);
smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1d, 2, ioapic_id, 0x12);
smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1d, 3, ioapic_id, 0x10);
smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1b, 0, ioapic_id, 0x10);
smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1c, 0, ioapic_id, 0x10);
smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1c, 1, ioapic_id, 0x11);
/* Firewire 4:0.0 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x4, 0x0, ioapic_id, 0x10);
smp_write_pci_intsrc(mc, mp_INT, 0x4, 0x00, 0, ioapic_id, 0x10);
// riser slot top 5:8.0
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x5, 0x20, ioapic_id, 0x14);
smp_write_pci_intsrc(mc, mp_INT, 0x5, 0x08, 0, ioapic_id, 0x14);
// riser slot middle 5:9.0
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x5, 0x24, ioapic_id, 0x15);
smp_write_pci_intsrc(mc, mp_INT, 0x5, 0x09, 0, ioapic_id, 0x15);
// riser slot bottom 5:a.0
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x5, 0x28, ioapic_id, 0x16);
smp_write_pci_intsrc(mc, mp_INT, 0x5, 0x0a, 0, ioapic_id, 0x16);
/* Onboard Ethernet */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x1, 0x0, ioapic_id, 0x10);
smp_write_pci_intsrc(mc, mp_INT, 0x1, 0x00, 0, ioapic_id, 0x10);
/* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
mptable_lintsrc(mc, isa_bus);

50
src/mainboard/ibase/mb899/mptable.c
View File

@ -57,52 +57,44 @@ static void *smp_write_config_table(void *v)
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xf, ioapic_id, 0xf);
/* Builtin devices on Bus 0 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x4, ioapic_id, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x8, ioapic_id, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x7d, ioapic_id, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x74, ioapic_id, 0x17);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x75, ioapic_id, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x76, ioapic_id, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x77, ioapic_id, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x6c, ioapic_id, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x70, ioapic_id, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x71, ioapic_id, 0x11);
smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x01, 0, ioapic_id, 0x10);
smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x02, 0, ioapic_id, 0x10);
smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1f, 1, ioapic_id, 0x13);
smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1d, 0, ioapic_id, 0x17);
smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1d, 1, ioapic_id, 0x13);
smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1d, 2, ioapic_id, 0x12);
smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1d, 3, ioapic_id, 0x10);
smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1b, 0, ioapic_id, 0x10);
smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1c, 0, ioapic_id, 0x10);
smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1c, 1, ioapic_id, 0x11);
/* Internal PCI bus (Firewire, PCI slot) */
if (firewire) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, firewire_bus, 0x0, ioapic_id,
0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, firewire_bus, 0x4, ioapic_id,
0x14);
smp_write_pci_intsrc(mc, mp_INT, firewire_bus, 0x00, 0, ioapic_id, 0x10);
smp_write_pci_intsrc(mc, mp_INT, firewire_bus, 0x01, 0, ioapic_id, 0x14);
}
if (riser) {
/* Old riser card */
// riser slot top 5:8.0
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, riser_bus, 0x20, ioapic_id,
0x14);
smp_write_pci_intsrc(mc, mp_INT, riser_bus, 0x08, 0, ioapic_id, 0x14);
// riser slot middle 5:9.0
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, riser_bus, 0x24, ioapic_id,
0x15);
smp_write_pci_intsrc(mc, mp_INT, riser_bus, 0x09, 0, ioapic_id, 0x15);
// riser slot bottom 5:a.0
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, riser_bus, 0x28, ioapic_id,
0x16);
smp_write_pci_intsrc(mc, mp_INT, riser_bus, 0x0a, 0, ioapic_id, 0x16);
/* New Riser Card */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, riser_bus, 0x30, ioapic_id,
0x14);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, riser_bus, 0x34, ioapic_id,
0x15);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, riser_bus, 0x38, ioapic_id,
0x16);
smp_write_pci_intsrc(mc, mp_INT, riser_bus, 0x0c, 0, ioapic_id, 0x14);
smp_write_pci_intsrc(mc, mp_INT, riser_bus, 0x0d, 0, ioapic_id, 0x15);
smp_write_pci_intsrc(mc, mp_INT, riser_bus, 0x0e, 0, ioapic_id, 0x16);
}
/* PCIe slot */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x1, 0x0, ioapic_id, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x1, 0x1, ioapic_id, 0x11);
smp_write_pci_intsrc(mc, mp_INT, 0x1, 0x00, 0, ioapic_id, 0x10);
smp_write_pci_intsrc(mc, mp_INT, 0x1, 0x00, 1, ioapic_id, 0x11);
/* Onboard Ethernet */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x2, 0x0, ioapic_id, 0x10);
smp_write_pci_intsrc(mc, mp_INT, 0x2, 0x00, 0, ioapic_id, 0x10);
/* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
mptable_lintsrc(mc, isa_bus);

34
src/mainboard/intel/d945gclf/mptable.c
View File

@ -25,34 +25,34 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0);
/* Builtin devices on Bus 0 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x8, ioapic_id, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x7d, ioapic_id, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x74, ioapic_id, 0x17);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x75, ioapic_id, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x76, ioapic_id, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x77, ioapic_id, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x6c, ioapic_id, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x70, ioapic_id, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x71, ioapic_id, 0x11);
smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x02, 0, ioapic_id, 0x10);
smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1f, 1, ioapic_id, 0x13);
smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1d, 0, ioapic_id, 0x17);
smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1d, 1, ioapic_id, 0x13);
smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1d, 2, ioapic_id, 0x12);
smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1d, 3, ioapic_id, 0x10);
smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1b, 0, ioapic_id, 0x10);
smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1c, 0, ioapic_id, 0x10);
smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1c, 1, ioapic_id, 0x11);
/* Firewire 4:0.0 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x4, 0x0, ioapic_id, 0x10);
smp_write_pci_intsrc(mc, mp_INT, 0x4, 0x00, 0, ioapic_id, 0x10);
/* Old riser card */
// riser slot top 5:8.0
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x5, 0x20, ioapic_id, 0x14);
smp_write_pci_intsrc(mc, mp_INT, 0x5, 0x08, 0, ioapic_id, 0x14);
// riser slot middle 5:9.0
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x5, 0x24, ioapic_id, 0x15);
smp_write_pci_intsrc(mc, mp_INT, 0x5, 0x09, 0, ioapic_id, 0x15);
// riser slot bottom 5:a.0
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x5, 0x28, ioapic_id, 0x16);
smp_write_pci_intsrc(mc, mp_INT, 0x5, 0x0a, 0, ioapic_id, 0x16);
/* New Riser Card */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x5, 0x30, ioapic_id, 0x14);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x5, 0x34, ioapic_id, 0x15);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x5, 0x38, ioapic_id, 0x16);
smp_write_pci_intsrc(mc, mp_INT, 0x5, 0x0c, 0, ioapic_id, 0x14);
smp_write_pci_intsrc(mc, mp_INT, 0x5, 0x0d, 0, ioapic_id, 0x15);
smp_write_pci_intsrc(mc, mp_INT, 0x5, 0x0e, 0, ioapic_id, 0x16);
/* Onboard Ethernet */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x1, 0x0, ioapic_id, 0x10);
smp_write_pci_intsrc(mc, mp_INT, 0x1, 0x00, 0, ioapic_id, 0x10);
/* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
mptable_lintsrc(mc, isa_bus);

50
src/mainboard/kontron/986lcd-m/mptable.c
View File

@ -39,52 +39,44 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0);
/* Builtin devices on Bus 0 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x4, ioapic_id, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x8, ioapic_id, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x7d, ioapic_id, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x74, ioapic_id, 0x17);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x75, ioapic_id, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x76, ioapic_id, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x77, ioapic_id, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x6c, ioapic_id, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x70, ioapic_id, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x71, ioapic_id, 0x11);
smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x01, 0, ioapic_id, 0x10);
smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x02, 0, ioapic_id, 0x10);
smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1f, 1, ioapic_id, 0x13);
smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1d, 0, ioapic_id, 0x17);
smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1d, 1, ioapic_id, 0x13);
smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1d, 2, ioapic_id, 0x12);
smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1d, 3, ioapic_id, 0x10);
smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1b, 0, ioapic_id, 0x10);
smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1c, 0, ioapic_id, 0x10);
smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1c, 1, ioapic_id, 0x11);
/* Internal PCI bus (Firewire, PCI slot) */
if (firewire) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, firewire_bus, 0x0, ioapic_id,
0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, firewire_bus, 0x4, ioapic_id,
0x14);
smp_write_pci_intsrc(mc, mp_INT, firewire_bus, 0x00, 0, ioapic_id, 0x10);
smp_write_pci_intsrc(mc, mp_INT, firewire_bus, 0x01, 0, ioapic_id, 0x14);
}
if (riser) {
/* Old riser card */
/* riser slot top 5:8.0 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, riser_bus, 0x20, ioapic_id,
0x14);
smp_write_pci_intsrc(mc, mp_INT, riser_bus, 0x08, 0, ioapic_id, 0x14);
/* riser slot middle 5:9.0 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, riser_bus, 0x24, ioapic_id,
0x15);
smp_write_pci_intsrc(mc, mp_INT, riser_bus, 0x09, 0, ioapic_id, 0x15);
/* riser slot bottom 5:a.0 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, riser_bus, 0x28, ioapic_id,
0x16);
smp_write_pci_intsrc(mc, mp_INT, riser_bus, 0x0a, 0, ioapic_id, 0x16);
/* New Riser Card */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, riser_bus, 0x30, ioapic_id,
0x14);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, riser_bus, 0x34, ioapic_id,
0x15);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, riser_bus, 0x38, ioapic_id,
0x16);
smp_write_pci_intsrc(mc, mp_INT, riser_bus, 0x0c, 0, ioapic_id, 0x14);
smp_write_pci_intsrc(mc, mp_INT, riser_bus, 0x0d, 0, ioapic_id, 0x15);
smp_write_pci_intsrc(mc, mp_INT, riser_bus, 0x0e, 0, ioapic_id, 0x16);
}
/* PCIe slot */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x1, 0x0, ioapic_id, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x1, 0x1, ioapic_id, 0x11);
smp_write_pci_intsrc(mc, mp_INT, 0x1, 0x00, 0, ioapic_id, 0x10);
smp_write_pci_intsrc(mc, mp_INT, 0x1, 0x00, 1, ioapic_id, 0x11);
/* Onboard Ethernet */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x2, 0x0, ioapic_id, 0x10);
smp_write_pci_intsrc(mc, mp_INT, 0x2, 0x00, 0, ioapic_id, 0x10);
/* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
mptable_lintsrc(mc, isa_bus);

28
src/mainboard/roda/rk886ex/mptable.c
View File

@ -24,28 +24,28 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0);
/* Builtin devices on Bus 0 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x8, ioapic_id, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x7d, ioapic_id, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x74, ioapic_id, 0x17);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x75, ioapic_id, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x76, ioapic_id, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x77, ioapic_id, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x6c, ioapic_id, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x70, ioapic_id, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x71, ioapic_id, 0x11);
smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x02, 0, ioapic_id, 0x10);
smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1f, 1, ioapic_id, 0x13);
smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1d, 0, ioapic_id, 0x17);
smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1d, 1, ioapic_id, 0x13);
smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1d, 2, ioapic_id, 0x12);
smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1d, 3, ioapic_id, 0x10);
smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1b, 0, ioapic_id, 0x10);
smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1c, 0, ioapic_id, 0x10);
smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1c, 1, ioapic_id, 0x11);
/* Firewire 4:0.0 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x4, 0x0, ioapic_id, 0x10);
smp_write_pci_intsrc(mc, mp_INT, 0x4, 0x00, 0, ioapic_id, 0x10);
/* riser slot top 5:8.0 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x5, 0x20, ioapic_id, 0x14);
smp_write_pci_intsrc(mc, mp_INT, 0x5, 0x08, 0, ioapic_id, 0x14);
/* riser slot middle 5:9.0 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x5, 0x24, ioapic_id, 0x15);
smp_write_pci_intsrc(mc, mp_INT, 0x5, 0x09, 0, ioapic_id, 0x15);
/* riser slot bottom 5:a.0 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x5, 0x28, ioapic_id, 0x16);
smp_write_pci_intsrc(mc, mp_INT, 0x5, 0x0a, 0, ioapic_id, 0x16);
/* Onboard Ethernet */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x1, 0x0, ioapic_id, 0x10);
smp_write_pci_intsrc(mc, mp_INT, 0x1, 0x00, 0, ioapic_id, 0x10);
/* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
mptable_lintsrc(mc, isa_bus);