AMD K8 fam10: Refactor Kconfig SB_HT_CHAIN_ON_BUS0
If SB_HT_CHAIN_ON_BUS0 is selected, HyperTransport chain for System Bus is the first to scan and it will be assigned with bus number 0. If HT_CHAIN_DISTRIBUTE is selected, each link will reserve a fixed range of bus numbers instead of assigning consecutive numbers across all the links. All fam10 have SB_HT_CHAIN_ON_BUS0 selected under northbridge. Follow-up can easily drop this if we find this is dictated by architecture. Change-Id: I8deddcb4c3fd679b6b27e2879d9dba3895c4dd6f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8366 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
This commit is contained in:
parent
98a915e262
commit
7748ee5ee1
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@ -52,10 +52,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC
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bool
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default n
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config SB_HT_CHAIN_ON_BUS0
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int
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default 1
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config HT_CHAIN_END_UNITID_BASE
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hex
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default 0x1
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@ -52,10 +52,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC
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bool
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default n
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config SB_HT_CHAIN_ON_BUS0
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int
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default 1
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config HT_CHAIN_END_UNITID_BASE
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hex
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default 0x1
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@ -36,10 +36,6 @@ config MAX_PHYSICAL_CPUS
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int
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default 1
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config SB_HT_CHAIN_ON_BUS0
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int
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default 1
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config HT_CHAIN_END_UNITID_BASE
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hex
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default 0x1
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@ -47,10 +47,6 @@ config MAX_PHYSICAL_CPUS
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int
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default 2
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config SB_HT_CHAIN_ON_BUS0
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int
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default 1
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config HT_CHAIN_END_UNITID_BASE
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hex
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default 0x1
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@ -40,10 +40,6 @@ config MAX_PHYSICAL_CPUS
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int
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default 2
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config SB_HT_CHAIN_ON_BUS0
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int
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default 1
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config HT_CHAIN_END_UNITID_BASE
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hex
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default 0x1
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@ -44,10 +44,6 @@ config MAX_PHYSICAL_CPUS
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int
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default 1
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config SB_HT_CHAIN_ON_BUS0
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int
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default 1
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config HT_CHAIN_END_UNITID_BASE
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hex
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default 0x1
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@ -10,6 +10,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select NORTHBRIDGE_AMD_AMDK8
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select SOUTHBRIDGE_AMD_AMD8111
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select SOUTHBRIDGE_AMD_AMD8131
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select HT_CHAIN_DISTRIBUTE
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select SUPERIO_WINBOND_W83627HF
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select PARALLEL_CPU_INIT
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select HAVE_OPTION_TABLE
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@ -55,10 +56,6 @@ config MEM_TRAIN_SEQ
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int
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default 1
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config SB_HT_CHAIN_ON_BUS0
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int
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default 2
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config HT_CHAIN_END_UNITID_BASE
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hex
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default 0x6
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@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select NORTHBRIDGE_AMD_AMDFAM10
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select SOUTHBRIDGE_AMD_AMD8111
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select SOUTHBRIDGE_AMD_AMD8132
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select HT_CHAIN_DISTRIBUTE
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select SUPERIO_WINBOND_W83627HF
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select HAVE_OPTION_TABLE
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select HAVE_PIRQ_TABLE
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@ -41,10 +42,6 @@ config MAX_PHYSICAL_CPUS
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int
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default 8
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config SB_HT_CHAIN_ON_BUS0
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int
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default 2
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config HT_CHAIN_END_UNITID_BASE
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hex
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default 0x6
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@ -40,10 +40,6 @@ config MAX_PHYSICAL_CPUS
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int
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default 2
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config SB_HT_CHAIN_ON_BUS0
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int
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default 1
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config HT_CHAIN_END_UNITID_BASE
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hex
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default 0x1
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@ -38,10 +38,6 @@ config MAX_PHYSICAL_CPUS
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int
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default 2
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config SB_HT_CHAIN_ON_BUS0
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int
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default 1
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config HT_CHAIN_END_UNITID_BASE
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hex
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default 0x20
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@ -49,10 +49,6 @@ config MAX_PHYSICAL_CPUS
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int
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default 2
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config SB_HT_CHAIN_ON_BUS0
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int
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default 1
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config HT_CHAIN_END_UNITID_BASE
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hex
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default 0x1
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@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select CPU_AMD_SOCKET_939
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select NORTHBRIDGE_AMD_AMDK8
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select SOUTHBRIDGE_NVIDIA_CK804
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select HT_CHAIN_DISTRIBUTE
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select SUPERIO_ITE_IT8712F
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select HAVE_OPTION_TABLE
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select HAVE_CMOS_DEFAULT
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@ -54,10 +55,6 @@ config HT_CHAIN_UNITID_BASE
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hex
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default 0x0
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config SB_HT_CHAIN_ON_BUS0
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int
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default 2
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config IRQ_SLOT_COUNT
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int
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default 13
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@ -33,10 +33,6 @@ config APIC_ID_OFFSET
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hex
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default 0x10
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config SB_HT_CHAIN_ON_BUS0
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int
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default 1
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config MAINBOARD_PART_NUMBER
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string
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default "A8V-E Deluxe"
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@ -33,10 +33,6 @@ config APIC_ID_OFFSET
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hex
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default 0x10
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config SB_HT_CHAIN_ON_BUS0
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int
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default 1
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config MAINBOARD_PART_NUMBER
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string
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default "A8V-E SE"
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@ -32,10 +32,6 @@ config APIC_ID_OFFSET
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hex
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default 0x10
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config SB_HT_CHAIN_ON_BUS0
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int
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default 1
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config MAINBOARD_PART_NUMBER
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string
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default "K8V-X"
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@ -44,10 +44,6 @@ config APIC_ID_OFFSET
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hex
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default 0
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config SB_HT_CHAIN_ON_BUS0
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int
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default 1
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config MAINBOARD_PART_NUMBER
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string
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default "KFSN4-DRE"
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@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select DIMM_DDR2
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select NORTHBRIDGE_AMD_AMDK8
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select SOUTHBRIDGE_NVIDIA_MCP55
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select HT_CHAIN_DISTRIBUTE
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select MCP55_USE_NIC
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select MCP55_USE_AZA
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select SUPERIO_ITE_IT8716F
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@ -57,10 +58,6 @@ config MEM_TRAIN_SEQ
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int
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default 2
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config SB_HT_CHAIN_ON_BUS0
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int
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default 2
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config MAINBOARD_PART_NUMBER
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string
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default "M2N-E"
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@ -67,10 +67,6 @@ config HT_CHAIN_UNITID_BASE
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hex
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default 0x0
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config SB_HT_CHAIN_ON_BUS0
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int
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default 1
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config HT_CHAIN_END_UNITID_BASE
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hex
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default 0x20
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@ -36,10 +36,6 @@ config APIC_ID_OFFSET
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hex
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default 0x10
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config SB_HT_CHAIN_ON_BUS0
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int
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default 1
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config MAINBOARD_PART_NUMBER
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string
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default "M2V"
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@ -39,10 +39,6 @@ config MAX_PHYSICAL_CPUS
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int
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default 2
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config SB_HT_CHAIN_ON_BUS0
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int
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default 1
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config HT_CHAIN_END_UNITID_BASE
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hex
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default 0x1
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@ -40,10 +40,6 @@ config MAX_PHYSICAL_CPUS
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int
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default 2
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config SB_HT_CHAIN_ON_BUS0
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int
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default 1
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config HT_CHAIN_END_UNITID_BASE
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hex
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default 0x1
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@ -42,10 +42,6 @@ config MAX_PHYSICAL_CPUS
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int
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default 2
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config SB_HT_CHAIN_ON_BUS0
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int
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default 1
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config HT_CHAIN_END_UNITID_BASE
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hex
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default 0x1
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@ -50,10 +50,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC
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bool
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default n
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config SB_HT_CHAIN_ON_BUS0
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int
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default 1
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config HT_CHAIN_END_UNITID_BASE
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hex
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default 0x1
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@ -52,10 +52,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC
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bool
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default n
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config SB_HT_CHAIN_ON_BUS0
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int
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default 1
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config HT_CHAIN_END_UNITID_BASE
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hex
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default 0x1
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@ -31,10 +31,6 @@ config APIC_ID_OFFSET
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hex
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default 0x0
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config SB_HT_CHAIN_ON_BUS0
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int
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default 1
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config MAINBOARD_PART_NUMBER
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string
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default "Blast"
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@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select DIMM_DDR2
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select NORTHBRIDGE_AMD_AMDK8
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select SOUTHBRIDGE_SIS_SIS966
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select HT_CHAIN_DISTRIBUTE
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select SUPERIO_ITE_IT8716F
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select PARALLEL_CPU_INIT
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select HAVE_OPTION_TABLE
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@ -37,10 +38,6 @@ config MEM_TRAIN_SEQ
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int
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default 2
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config SB_HT_CHAIN_ON_BUS0
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int
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default 2
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config MAINBOARD_PART_NUMBER
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string
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default "GA-2761GXDK"
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@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select DIMM_DDR2
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select NORTHBRIDGE_AMD_AMDK8
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select SOUTHBRIDGE_NVIDIA_MCP55
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select HT_CHAIN_DISTRIBUTE
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select MCP55_USE_NIC
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select MCP55_USE_AZA
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select SUPERIO_ITE_IT8716F
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@ -41,10 +42,6 @@ config MEM_TRAIN_SEQ
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int
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default 2
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config SB_HT_CHAIN_ON_BUS0
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int
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default 2
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config MAINBOARD_PART_NUMBER
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string
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default "GA-M57SLI-S4"
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@ -40,10 +40,6 @@ config MAX_PHYSICAL_CPUS
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int
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default 2
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config SB_HT_CHAIN_ON_BUS0
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int
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default 1
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config HT_CHAIN_END_UNITID_BASE
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hex
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default 0x1
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@ -40,10 +40,6 @@ config MAX_PHYSICAL_CPUS
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int
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default 2
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config SB_HT_CHAIN_ON_BUS0
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int
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default 1
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config HT_CHAIN_END_UNITID_BASE
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hex
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default 0x1
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@ -40,10 +40,6 @@ config MAX_PHYSICAL_CPUS
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int
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default 2
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config SB_HT_CHAIN_ON_BUS0
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int
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default 1
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config HT_CHAIN_END_UNITID_BASE
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hex
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default 0x1
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@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select NORTHBRIDGE_AMD_AMDK8
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select SOUTHBRIDGE_AMD_AMD8131
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select SOUTHBRIDGE_AMD_AMD8111
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select HT_CHAIN_DISTRIBUTE
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select SUPERIO_WINBOND_W83627HF
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select HAVE_HARD_RESET
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select HAVE_OPTION_TABLE
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@ -28,10 +29,6 @@ config APIC_ID_OFFSET
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hex
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default 0x0
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config SB_HT_CHAIN_ON_BUS0
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int
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default 2
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config MAINBOARD_PART_NUMBER
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string
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default "ProLiant DL145 G1"
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@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select NORTHBRIDGE_AMD_AMDK8
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select SOUTHBRIDGE_BROADCOM_BCM21000
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select SOUTHBRIDGE_BROADCOM_BCM5785
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select HT_CHAIN_DISTRIBUTE
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select SUPERIO_SERVERENGINES_PILOT
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select SUPERIO_NSC_PC87417
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select HAVE_OPTION_TABLE
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@ -56,10 +57,6 @@ config HT_CHAIN_UNITID_BASE
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hex
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default 0x6
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config SB_HT_CHAIN_ON_BUS0
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int
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default 2
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config IRQ_SLOT_COUNT
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int
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default 15
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@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select NORTHBRIDGE_AMD_AMDFAM10
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select SOUTHBRIDGE_BROADCOM_BCM21000
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select SOUTHBRIDGE_BROADCOM_BCM5785
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select HT_CHAIN_DISTRIBUTE
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select SUPERIO_SERVERENGINES_PILOT
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select SUPERIO_NSC_PC87417
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select DIMM_DDR2
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@ -55,10 +56,6 @@ config HT_CHAIN_UNITID_BASE
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hex
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default 0x6
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config SB_HT_CHAIN_ON_BUS0
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int
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default 2
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config IRQ_SLOT_COUNT
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int
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default 15
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@ -40,10 +40,6 @@ config MAX_PHYSICAL_CPUS
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int
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default 2
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config SB_HT_CHAIN_ON_BUS0
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int
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default 1
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config HT_CHAIN_END_UNITID_BASE
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hex
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default 0x1
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@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select NORTHBRIDGE_AMD_AMDK8
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select SOUTHBRIDGE_AMD_AMD8111
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select SOUTHBRIDGE_AMD_AMD8131
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select HT_CHAIN_DISTRIBUTE
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select SUPERIO_WINBOND_W83627HF
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select PARALLEL_CPU_INIT
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select HAVE_OPTION_TABLE
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@ -38,10 +39,6 @@ config MAX_PHYSICAL_CPUS
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int
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default 2
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config SB_HT_CHAIN_ON_BUS0
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int
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default 2
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config HT_CHAIN_END_UNITID_BASE
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hex
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default 0x6
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@ -40,10 +40,6 @@ config MAX_PHYSICAL_CPUS
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int
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default 2
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config SB_HT_CHAIN_ON_BUS0
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int
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default 1
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config HT_CHAIN_END_UNITID_BASE
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hex
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default 0x1
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@ -37,10 +37,6 @@ config MAX_PHYSICAL_CPUS
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int
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default 1
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config SB_HT_CHAIN_ON_BUS0
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int
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default 1
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config HT_CHAIN_END_UNITID_BASE
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hex
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default 0x1
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@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select CPU_AMD_SOCKET_754
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select NORTHBRIDGE_AMD_AMDK8
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select SOUTHBRIDGE_NVIDIA_CK804
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select HT_CHAIN_DISTRIBUTE
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select SUPERIO_WINBOND_W83627THG
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select HAVE_OPTION_TABLE
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select HAVE_PIRQ_TABLE
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@ -43,10 +44,6 @@ config HT_CHAIN_END_UNITID_BASE
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hex
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default 0x20
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config SB_HT_CHAIN_ON_BUS0
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int
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default 2
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config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 13
|
||||
|
|
|
@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
|
|||
select DIMM_DDR2
|
||||
select NORTHBRIDGE_AMD_AMDK8
|
||||
select SOUTHBRIDGE_NVIDIA_MCP55
|
||||
select HT_CHAIN_DISTRIBUTE
|
||||
select MCP55_USE_NIC
|
||||
select MCP55_USE_AZA
|
||||
select SUPERIO_WINBOND_W83627EHG
|
||||
|
@ -39,10 +40,6 @@ config MEM_TRAIN_SEQ
|
|||
int
|
||||
default 2
|
||||
|
||||
config SB_HT_CHAIN_ON_BUS0
|
||||
int
|
||||
default 2
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "MS-7260"
|
||||
|
|
|
@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
|
|||
select NORTHBRIDGE_AMD_AMDK8
|
||||
select SOUTHBRIDGE_BROADCOM_BCM5780
|
||||
select SOUTHBRIDGE_BROADCOM_BCM5785
|
||||
select HT_CHAIN_DISTRIBUTE
|
||||
select SUPERIO_NSC_PC87417
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_PIRQ_TABLE
|
||||
|
@ -34,10 +35,6 @@ config APIC_ID_OFFSET
|
|||
hex
|
||||
default 0x8
|
||||
|
||||
config SB_HT_CHAIN_ON_BUS0
|
||||
int
|
||||
default 2
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "MS-9185"
|
||||
|
|
|
@ -33,10 +33,6 @@ config APIC_ID_OFFSET
|
|||
hex
|
||||
default 0x10
|
||||
|
||||
config SB_HT_CHAIN_ON_BUS0
|
||||
int
|
||||
default 1
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "MS-9282"
|
||||
|
|
|
@ -76,10 +76,6 @@ config HT_CHAIN_END_UNITID_BASE
|
|||
hex
|
||||
default 0x00
|
||||
|
||||
config SB_HT_CHAIN_ON_BUS0
|
||||
int
|
||||
default 1
|
||||
|
||||
config VAR_MTRR_HOLE
|
||||
bool
|
||||
default n
|
||||
|
|
|
@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
|
|||
select DIMM_REGISTERED
|
||||
select NORTHBRIDGE_AMD_AMDK8
|
||||
select SOUTHBRIDGE_NVIDIA_MCP55
|
||||
select HT_CHAIN_DISTRIBUTE
|
||||
select MCP55_USE_NIC
|
||||
select MCP55_USE_AZA
|
||||
select SUPERIO_WINBOND_W83627EHG
|
||||
|
@ -43,10 +44,6 @@ config MCP55_NUM
|
|||
int
|
||||
default 2
|
||||
|
||||
config SB_HT_CHAIN_ON_BUS0
|
||||
int
|
||||
default 2
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "l1_2pvv"
|
||||
|
|
|
@ -43,10 +43,6 @@ config MAX_PHYSICAL_CPUS
|
|||
int
|
||||
default 1
|
||||
|
||||
config SB_HT_CHAIN_ON_BUS0
|
||||
int
|
||||
default 1
|
||||
|
||||
config HT_CHAIN_END_UNITID_BASE
|
||||
hex
|
||||
default 0x1
|
||||
|
|
|
@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
|
|||
select CPU_AMD_SOCKET_940
|
||||
select NORTHBRIDGE_AMD_AMDK8
|
||||
select SOUTHBRIDGE_NVIDIA_CK804
|
||||
select HT_CHAIN_DISTRIBUTE
|
||||
select SUPERIO_SMSC_LPC47B397
|
||||
select SUPERIO_SMSC_LPC47M10X
|
||||
select HAVE_OPTION_TABLE
|
||||
|
@ -56,10 +57,6 @@ config HT_CHAIN_UNITID_BASE
|
|||
hex
|
||||
default 0x0
|
||||
|
||||
config SB_HT_CHAIN_ON_BUS0
|
||||
int
|
||||
default 2
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 11
|
||||
|
|
|
@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
|
|||
select DIMM_REGISTERED
|
||||
select NORTHBRIDGE_AMD_AMDK8
|
||||
select SOUTHBRIDGE_NVIDIA_MCP55
|
||||
select HT_CHAIN_DISTRIBUTE
|
||||
select MCP55_USE_NIC
|
||||
select MCP55_USE_AZA
|
||||
select SUPERIO_WINBOND_W83627HF
|
||||
|
@ -60,10 +61,6 @@ config HT_CHAIN_UNITID_BASE
|
|||
hex
|
||||
default 0x0
|
||||
|
||||
config SB_HT_CHAIN_ON_BUS0
|
||||
int
|
||||
default 2
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 11
|
||||
|
|
|
@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
|
|||
select DIMM_REGISTERED
|
||||
select NORTHBRIDGE_AMD_AMDK8
|
||||
select SOUTHBRIDGE_NVIDIA_MCP55
|
||||
select HT_CHAIN_DISTRIBUTE
|
||||
select MCP55_USE_NIC
|
||||
select MCP55_USE_AZA
|
||||
select SUPERIO_WINBOND_W83627HF
|
||||
|
@ -59,10 +60,6 @@ config HT_CHAIN_UNITID_BASE
|
|||
hex
|
||||
default 0x0
|
||||
|
||||
config SB_HT_CHAIN_ON_BUS0
|
||||
int
|
||||
default 2
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 11
|
||||
|
|
|
@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
|
|||
select DIMM_REGISTERED
|
||||
select NORTHBRIDGE_AMD_AMDFAM10
|
||||
select SOUTHBRIDGE_NVIDIA_MCP55
|
||||
select HT_CHAIN_DISTRIBUTE
|
||||
select MCP55_USE_NIC
|
||||
select MCP55_USE_AZA
|
||||
select SUPERIO_WINBOND_W83627HF
|
||||
|
@ -55,10 +56,6 @@ config HT_CHAIN_UNITID_BASE
|
|||
hex
|
||||
default 0x1
|
||||
|
||||
config SB_HT_CHAIN_ON_BUS0
|
||||
int
|
||||
default 2
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 11
|
||||
|
|
|
@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
|
|||
select NORTHBRIDGE_AMD_AMDFAM10
|
||||
select SOUTHBRIDGE_AMD_AMD8132
|
||||
select SOUTHBRIDGE_NVIDIA_MCP55
|
||||
select HT_CHAIN_DISTRIBUTE
|
||||
select SUPERIO_WINBOND_W83627HF
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_PIRQ_TABLE
|
||||
|
@ -53,10 +54,6 @@ config HT_CHAIN_UNITID_BASE
|
|||
hex
|
||||
default 0x1
|
||||
|
||||
config SB_HT_CHAIN_ON_BUS0
|
||||
int
|
||||
default 2
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 11
|
||||
|
|
|
@ -40,10 +40,6 @@ config MAX_PHYSICAL_CPUS
|
|||
int
|
||||
default 1
|
||||
|
||||
config SB_HT_CHAIN_ON_BUS0
|
||||
int
|
||||
default 1
|
||||
|
||||
config HT_CHAIN_END_UNITID_BASE
|
||||
hex
|
||||
default 0x1
|
||||
|
|
|
@ -37,10 +37,6 @@ config MAX_PHYSICAL_CPUS
|
|||
int
|
||||
default 1
|
||||
|
||||
config SB_HT_CHAIN_ON_BUS0
|
||||
int
|
||||
default 1
|
||||
|
||||
config HT_CHAIN_END_UNITID_BASE
|
||||
hex
|
||||
default 0x1
|
||||
|
|
|
@ -36,10 +36,6 @@ config MAX_PHYSICAL_CPUS
|
|||
int
|
||||
default 1
|
||||
|
||||
config SB_HT_CHAIN_ON_BUS0
|
||||
int
|
||||
default 1
|
||||
|
||||
config HT_CHAIN_END_UNITID_BASE
|
||||
hex
|
||||
default 0x1
|
||||
|
|
|
@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
|
|||
select NORTHBRIDGE_AMD_AMDK8
|
||||
select SOUTHBRIDGE_AMD_AMD8131
|
||||
select SOUTHBRIDGE_AMD_AMD8111
|
||||
select HT_CHAIN_DISTRIBUTE
|
||||
select SUPERIO_WINBOND_W83627HF
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_PIRQ_TABLE
|
||||
|
@ -24,10 +25,6 @@ config APIC_ID_OFFSET
|
|||
hex
|
||||
default 0x0
|
||||
|
||||
config SB_HT_CHAIN_ON_BUS0
|
||||
int
|
||||
default 2
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "S2881"
|
||||
|
|
|
@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
|
|||
select SOUTHBRIDGE_AMD_AMD8111
|
||||
select SOUTHBRIDGE_AMD_AMD8131
|
||||
select SOUTHBRIDGE_AMD_AMD8151
|
||||
select HT_CHAIN_DISTRIBUTE
|
||||
select SUPERIO_WINBOND_W83627HF
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_PIRQ_TABLE
|
||||
|
@ -23,10 +24,6 @@ config APIC_ID_OFFSET
|
|||
hex
|
||||
default 0x10
|
||||
|
||||
config SB_HT_CHAIN_ON_BUS0
|
||||
int
|
||||
default 2
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "S2885"
|
||||
|
|
|
@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
|
|||
select NORTHBRIDGE_AMD_AMDK8
|
||||
select SOUTHBRIDGE_NVIDIA_CK804
|
||||
select SOUTHBRIDGE_AMD_AMD8131
|
||||
select HT_CHAIN_DISTRIBUTE
|
||||
select SUPERIO_WINBOND_W83627HF
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_PIRQ_TABLE
|
||||
|
@ -23,10 +24,6 @@ config APIC_ID_OFFSET
|
|||
hex
|
||||
default 0x10
|
||||
|
||||
config SB_HT_CHAIN_ON_BUS0
|
||||
int
|
||||
default 2
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "S2891"
|
||||
|
|
|
@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
|
|||
select NORTHBRIDGE_AMD_AMDK8
|
||||
select SOUTHBRIDGE_NVIDIA_CK804
|
||||
select SOUTHBRIDGE_AMD_AMD8131
|
||||
select HT_CHAIN_DISTRIBUTE
|
||||
select SUPERIO_WINBOND_W83627HF
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_PIRQ_TABLE
|
||||
|
@ -43,10 +44,6 @@ config HT_CHAIN_END_UNITID_BASE
|
|||
hex
|
||||
default 0x20
|
||||
|
||||
config SB_HT_CHAIN_ON_BUS0
|
||||
int
|
||||
default 2
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 11
|
||||
|
|
|
@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
|
|||
select NORTHBRIDGE_AMD_AMDK8
|
||||
select SOUTHBRIDGE_NVIDIA_CK804
|
||||
select SOUTHBRIDGE_AMD_AMD8131
|
||||
select HT_CHAIN_DISTRIBUTE
|
||||
select SUPERIO_SMSC_LPC47B397
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_PIRQ_TABLE
|
||||
|
@ -47,10 +48,6 @@ config HT_CHAIN_END_UNITID_BASE
|
|||
hex
|
||||
default 0x20
|
||||
|
||||
config SB_HT_CHAIN_ON_BUS0
|
||||
int
|
||||
default 2
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 11
|
||||
|
|
|
@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
|
|||
select DIMM_REGISTERED
|
||||
select NORTHBRIDGE_AMD_AMDK8
|
||||
select SOUTHBRIDGE_NVIDIA_MCP55
|
||||
select HT_CHAIN_DISTRIBUTE
|
||||
select MCP55_USE_NIC
|
||||
select SUPERIO_WINBOND_W83627HF
|
||||
select PARALLEL_CPU_INIT
|
||||
|
@ -38,10 +39,6 @@ config MEM_TRAIN_SEQ
|
|||
int
|
||||
default 1
|
||||
|
||||
config SB_HT_CHAIN_ON_BUS0
|
||||
int
|
||||
default 2
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "S2912"
|
||||
|
|
|
@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
|
|||
select DIMM_REGISTERED
|
||||
select NORTHBRIDGE_AMD_AMDFAM10
|
||||
select SOUTHBRIDGE_NVIDIA_MCP55
|
||||
select HT_CHAIN_DISTRIBUTE
|
||||
select MCP55_USE_NIC
|
||||
select SUPERIO_WINBOND_W83627HF
|
||||
select PARALLEL_CPU_INIT
|
||||
|
@ -35,10 +36,6 @@ config APIC_ID_OFFSET
|
|||
hex
|
||||
default 0
|
||||
|
||||
config SB_HT_CHAIN_ON_BUS0
|
||||
int
|
||||
default 2
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "S2912 (Fam10)"
|
||||
|
|
|
@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
|
|||
select CPU_AMD_SOCKET_940
|
||||
select NORTHBRIDGE_AMD_AMDK8
|
||||
select SOUTHBRIDGE_NVIDIA_CK804
|
||||
select HT_CHAIN_DISTRIBUTE
|
||||
select SUPERIO_WINBOND_W83627THG
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_PIRQ_TABLE
|
||||
|
@ -25,10 +26,6 @@ config APIC_ID_OFFSET
|
|||
hex
|
||||
default 0x10
|
||||
|
||||
config SB_HT_CHAIN_ON_BUS0
|
||||
int
|
||||
default 2
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "MB6047"
|
||||
|
|
|
@ -64,6 +64,12 @@ config SB_HT_CHAIN_UNITID_OFFSET_ONLY
|
|||
bool
|
||||
default n
|
||||
|
||||
config SB_HT_CHAIN_ON_BUS0
|
||||
def_bool y
|
||||
|
||||
config HT_CHAIN_DISTRIBUTE
|
||||
def_bool n
|
||||
|
||||
config DIMM_FBDIMM
|
||||
bool
|
||||
default n
|
||||
|
|
|
@ -216,11 +216,11 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool
|
|||
* so we set the subordinate bus number to 0xff for the moment.
|
||||
*/
|
||||
|
||||
if ((CONFIG_SB_HT_CHAIN_ON_BUS0 == 0) || !is_sblink)
|
||||
if (!CONFIG_SB_HT_CHAIN_ON_BUS0 || !is_sblink)
|
||||
max++;
|
||||
|
||||
/* One node can have 8 link and segn is the same. */
|
||||
if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 1) && !is_sblink)
|
||||
if (CONFIG_HT_CHAIN_DISTRIBUTE && !is_sblink)
|
||||
max = ALIGN_UP(max, 8);
|
||||
|
||||
link->secondary = max;
|
||||
|
|
|
@ -65,8 +65,10 @@ config SB_HT_CHAIN_UNITID_OFFSET_ONLY
|
|||
default n
|
||||
|
||||
config SB_HT_CHAIN_ON_BUS0
|
||||
int
|
||||
default 0
|
||||
def_bool y
|
||||
|
||||
config HT_CHAIN_DISTRIBUTE
|
||||
def_bool n
|
||||
|
||||
config QRANK_DIMM_SUPPORT
|
||||
bool
|
||||
|
|
|
@ -179,11 +179,11 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_
|
|||
* so we set the subordinate bus number to 0xff for the moment.
|
||||
*/
|
||||
|
||||
if ((CONFIG_SB_HT_CHAIN_ON_BUS0 == 0) || !is_sblink)
|
||||
if (!CONFIG_SB_HT_CHAIN_ON_BUS0 || !is_sblink)
|
||||
max++;
|
||||
|
||||
/* Second chain will be on 0x40, third 0x80, forth 0xc0. */
|
||||
if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 1) && !is_sblink)
|
||||
if (CONFIG_HT_CHAIN_DISTRIBUTE && !is_sblink)
|
||||
max = ALIGN_UP(max, 0x40);
|
||||
|
||||
link->secondary = max;
|
||||
|
|
Loading…
Reference in New Issue