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nb/intel/sandybridge: Correct late DMI init sequence 

Based on reference code, update the DMI ASPM setup steps.

Change-Id: I1248305b2f76f48f4e6910de1a6980e942f16945
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48536
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-12-10 16:43:25 +01:00 committed by Patrick Georgi
parent e515515e2e
commit 77516ca792
1 changed files with 23 additions and 11 deletions
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34
src/northbridge/intel/sandybridge/northbridge.c
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@ -256,17 +256,15 @@ static void northbridge_dmi_init(struct device *dev)
{ {
const bool is_sandy = is_sandybridge(); const bool is_sandy = is_sandybridge();
u32 reg32; const u8 stepping = cpu_stepping();
/* Clear error status bits */ u32 reg32;
DMIBAR32(DMIUESTS) = 0xffffffff;
DMIBAR32(DMICESTS) = 0xffffffff;
/* Steps prior to DMI ASPM */ /* Steps prior to DMI ASPM */
if (is_sandy) { if (is_sandy) {
reg32 = DMIBAR32(0x250); reg32 = DMIBAR32(0x250);
reg32 &= ~((1 << 22) | (1 << 20)); reg32 &= ~(7 << 20);
reg32 |= (1 << 21); reg32 |= (2 << 20);
DMIBAR32(0x250) = reg32; DMIBAR32(0x250) = reg32;
} }
@ -274,12 +272,14 @@ static void northbridge_dmi_init(struct device *dev)
reg32 |= (1 << 29); reg32 |= (1 << 29);
DMIBAR32(DMILLTC) = reg32; DMIBAR32(DMILLTC) = reg32;
if (!is_sandy || cpu_stepping() >= SNB_STEP_D0) { if (is_sandy && stepping == SNB_STEP_C0) {
reg32 = DMIBAR32(0x1f8); reg32 = DMIBAR32(0xbc8);
reg32 |= (1 << 16); reg32 &= ~(0xfff << 7);
DMIBAR32(0x1f8) = reg32; reg32 |= (0x7d3 << 7);
DMIBAR32(0xbc8) = reg32;
}
} else if (!is_sandy || cpu_stepping() >= SNB_STEP_D1) { if (!is_sandy || stepping >= SNB_STEP_D1) {
reg32 = DMIBAR32(0x1f8); reg32 = DMIBAR32(0x1f8);
reg32 &= ~(1 << 26); reg32 &= ~(1 << 26);
reg32 |= (1 << 16); reg32 |= (1 << 16);
@ -288,8 +288,20 @@ static void northbridge_dmi_init(struct device *dev)
reg32 = DMIBAR32(0x1fc); reg32 = DMIBAR32(0x1fc);
reg32 |= (1 << 12) | (1 << 23); reg32 |= (1 << 12) | (1 << 23);
DMIBAR32(0x1fc) = reg32; DMIBAR32(0x1fc) = reg32;
} else if (stepping >= SNB_STEP_D0) {
reg32 = DMIBAR32(0x1f8);
reg32 |= (1 << 16);
DMIBAR32(0x1f8) = reg32;
} }
/* Clear error status bits */
DMIBAR32(DMIUESTS) = 0xffffffff;
DMIBAR32(DMICESTS) = 0xffffffff;
if (!is_sandy)
DMIBAR32(0xc34) = 0xffffffff;
/* Enable ASPM on SNB link, should happen before PCH link */ /* Enable ASPM on SNB link, should happen before PCH link */
if (is_sandy) { if (is_sandy) {
reg32 = DMIBAR32(0xd04); reg32 = DMIBAR32(0xd04);