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Remove fallback/normal handling in mainboards' 

romstage.c like r5255 did for failover/fallback/normal
mainboards.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5257 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Patrick Georgi 2010-03-18 16:18:58 +00:00
parent a41b939294
commit 776b85ba45
46 changed files with 256 additions and 2181 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
src/arch/i386/Makefile.inc
View File

@ -87,7 +87,6 @@ $(obj)/coreboot.a: $(objs)
crt0s :=
ldscripts :=
ldscripts += $(src)/arch/i386/init/ldscript_fallback_cbfs.lb
ldscripts += $(src)/arch/i386/lib/failover.lds
ifeq ($(CONFIG_BIG_BOOTBLOCK),y)
crt0s += $(src)/cpu/x86/16bit/entry16.inc
ldscripts += $(src)/cpu/x86/16bit/entry16.lds
@ -160,12 +159,6 @@ crt0s += $(src)/cpu/x86/car/cache_as_ram.inc
ldscripts += $(src)/cpu/x86/car/cache_as_ram.lds
endif
ifeq ($(CONFIG_BIG_BOOTBLOCK),y)
ifeq ($(CONFIG_ROMCC),y)
crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/failover.inc
endif
endif
ifeq ($(CONFIG_LLSHELL),y)
crt0s += $(src)/arch/i386/llshell/llshell.inc
endif
@ -196,10 +189,6 @@ endif
ifeq ($(CONFIG_ROMCC),y)
ROMCCFLAGS ?= -mcpu=p2 -O2
$(obj)/mainboard/$(MAINBOARDDIR)/failover.inc: $(obj)/romcc $(src)/arch/i386/lib/failover.c
printf " ROMCC failover.inc\n"
$(obj)/romcc $(ROMCCFLAGS) --label-prefix=failover $(INCLUDES) $(src)/arch/i386/lib/failover.c -o $@
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/romcc $(OPTION_TABLE_H) $(obj)/build.h
printf " ROMCC romstage.inc\n"
$(obj)/romcc $(ROMCCFLAGS) -include $(obj)/build.h $(INCLUDES) $< -o $@

50
src/arch/i386/lib/failover.c
View File

@ -1,50 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#define __PRE_RAM__
#include <arch/io.h>
#include "arch/romcc_io.h"
#include "pc80/mc146818rtc_early.c"
/**
* Check whether the normal or the fallback image should be booted
* (by reading the proper flag from CMOS), and boot it.
*
* @param bist The input BIST value.
* @return The BIST value.
*/
static unsigned long main(unsigned long bist)
{
if (do_normal_boot())
goto normal_image;
else
goto fallback_image;
normal_image:
__asm__ __volatile__("jmp __normal_image" : : "a" (bist) : );
cpu_reset:
__asm__ __volatile__("jmp __cpu_reset" : : "a" (bist) : );
fallback_image:
return bist;
}

1
src/arch/i386/lib/failover.lds
View File

@ -1 +0,0 @@
__normal_image = (CONFIG_ROMBASE & 0xfffffff0) - 8;

24
src/cpu/intel/model_106cx/cache_as_ram_disable.c
View File

@ -25,30 +25,6 @@ void stage1_main(unsigned long bist)
{
unsigned int cpu_reset = 0;
#if !defined(CONFIG_TINY_BOOTBLOCK) || !CONFIG_TINY_BOOTBLOCK
#if CONFIG_USE_FALLBACK_IMAGE == 1
/* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal()) {
goto normal_image;
} else {
/* This is the primary cpu how should I boot? */
check_cmos_failed();
if (do_normal_boot()) {
goto normal_image;
}
else {
goto fallback_image;
}
}
normal_image:
__asm__ volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist) /* inputs */
);
fallback_image:
#endif
#endif
real_main(bist);
/* No servicable parts below this line .. */

24
src/cpu/intel/model_6ex/cache_as_ram_disable.c
View File

@ -27,30 +27,6 @@ void stage1_main(unsigned long bist)
{
unsigned int cpu_reset = 0;
#if !defined(CONFIG_TINY_BOOTBLOCK) || !CONFIG_TINY_BOOTBLOCK
#if CONFIG_USE_FALLBACK_IMAGE == 1
/* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal()) {
goto normal_image;
} else {
/* This is the primary cpu how should I boot? */
check_cmos_failed();
if (do_normal_boot()) {
goto normal_image;
}
else {
goto fallback_image;
}
}
normal_image:
__asm__ volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist) /* inputs */
);
fallback_image:
#endif
#endif
real_main(bist);
/* No servicable parts below this line .. */

24
src/cpu/intel/model_6fx/cache_as_ram_disable.c
View File

@ -27,30 +27,6 @@ void stage1_main(unsigned long bist)
{
unsigned int cpu_reset = 0;
#if !defined(CONFIG_TINY_BOOTBLOCK) || !CONFIG_TINY_BOOTBLOCK
#if CONFIG_USE_FALLBACK_IMAGE == 1
/* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal()) {
goto normal_image;
} else {
/* This is the primary cpu how should I boot? */
check_cmos_failed();
if (do_normal_boot()) {
goto normal_image;
}
else {
goto fallback_image;
}
}
normal_image:
__asm__ volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist) /* inputs */
);
fallback_image:
#endif
#endif
real_main(bist);
/* No servicable parts below this line .. */

58
src/mainboard/amd/dbm690t/romstage.c
View File

@ -100,59 +100,9 @@ static inline int spd_read_byte(u32 device, u32 address)
#include "cpu/amd/model_fxx/fidvid.c"
#if CONFIG_USE_FALLBACK_IMAGE == 1
#include "northbridge/amd/amdk8/early_ht.c"
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
{
/* Is this a cpu only reset? Is this a secondary cpu? */
if ((cpu_init_detectedx) || (!boot_cpu())) {
if (last_boot_normal()) { /* RTC already inited */
goto normal_image;
} else {
goto fallback_image;
}
}
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* sb600_lpc_port80(); */
sb600_pci_port80();
/* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal()) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
goto normal_image;
} else {
goto fallback_image;
}
normal_image:
post_code(0x23);
__asm__ volatile ("jmp __normal_image": /* outputs */
:"a" (bist), "b"(cpu_init_detectedx) /* inputs */);
fallback_image:
post_code(0x25);
}
#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
#if CONFIG_USE_FALLBACK_IMAGE == 1
failover_process(bist, cpu_init_detectedx);
#endif
real_main(bist, cpu_init_detectedx);
}
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
int needs_reset = 0;
@ -161,6 +111,14 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
struct cpuid_result cpuid1;
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
if (!((cpu_init_detectedx) || (!boot_cpu()))) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* sb600_lpc_port80(); */
sb600_pci_port80();
}
if (bist == 0) {
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);

239
src/mainboard/amd/mahogany/cache_as_ram_auto.c
View File

@ -1,239 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define K8_SET_FIDVID 1
#define QRANK_DIMM_SUPPORT 1
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif
#define RC0 (6<<8)
#define RC1 (7<<8)
#define DIMM0 0x50
#define DIMM1 0x51
#define ICS951462_ADDRESS 0x69
#define SMBUS_HUB 0x71
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#define post_code(x) outb(x, 0x80)
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/ite/it8718f/it8718f_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/amd/rs780/rs780_early_setup.c"
#include "southbridge/amd/sb700/sb700_early_setup.c"
/* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
/* called in raminit_f.c */
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
}
/*called in raminit_f.c */
static inline int spd_read_byte(u32 device, u32 address)
{
return smbus_read_byte(device, address);
}
#include "northbridge/amd/amdk8/amdk8.h"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include "cpu/amd/car/copy_and_run.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
#include "cpu/amd/model_fxx/fidvid.c"
#if CONFIG_USE_FALLBACK_IMAGE == 1
#include "northbridge/amd/amdk8/early_ht.c"
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
{
/* Is this a cpu only reset? Is this a secondary cpu? */
if ((cpu_init_detectedx) || (!boot_cpu())) {
if (last_boot_normal()) { /* RTC already inited */
goto normal_image;
} else {
goto fallback_image;
}
}
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* sb700_lpc_port80(); */
sb700_pci_port80();
/* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal()) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
goto normal_image;
} else {
goto fallback_image;
}
normal_image:
post_code(0x23);
__asm__ volatile ("jmp __normal_image": /* outputs */
:"a" (bist), "b"(cpu_init_detectedx) /* inputs */);
fallback_image:
post_code(0x25);
}
#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
#if CONFIG_USE_FALLBACK_IMAGE == 1
failover_process(bist, cpu_init_detectedx);
#endif
real_main(bist, cpu_init_detectedx);
}
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
int needs_reset = 0;
u32 bsp_apicid = 0;
msr_t msr;
struct cpuid_result cpuid1;
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
if (bist == 0) {
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
}
enable_rs780_dev8();
sb700_lpc_init();
it8718f_enable_serial(0, CONFIG_TTYS0_BASE);
uart_init();
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
printk_debug("bsp_apicid=0x%x\n", bsp_apicid);
setup_mahogany_resource_map();
setup_coherent_ht_domain();
#if CONFIG_LOGICAL_CPUS==1
/* It is said that we should start core1 after all core0 launched */
wait_all_core0_started();
start_other_cores();
#endif
wait_all_aps_started(bsp_apicid);
ht_setup_chains_x(sysinfo);
/* run _early_setup before soft-reset. */
rs780_early_setup();
sb700_early_setup();
/* Check to see if processor is capable of changing FIDVID */
/* otherwise it will throw a GP# when reading FIDVID_STATUS */
cpuid1 = cpuid(0x80000007);
if( (cpuid1.edx & 0x6) == 0x6 ) {
/* Read FIDVID_STATUS */
msr=rdmsr(0xc0010042);
printk_debug("begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
init_fidvid_bsp(bsp_apicid);
/* show final fid and vid */
msr=rdmsr(0xc0010042);
printk_debug("end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
} else {
printk_debug("Changing FIDVID not supported\n");
}
needs_reset = optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo);
rs780_htinit();
printk_debug("needs_reset=0x%x\n", needs_reset);
if (needs_reset) {
print_info("ht reset -\r\n");
soft_reset();
}
allow_all_aps_stop(bsp_apicid);
/* It's the time to set ctrl now; */
printk_debug("sysinfo->nodes: %2x sysinfo->ctrl: %2x spd_addr: %2x\n",
sysinfo->nodes, sysinfo->ctrl, spd_addr);
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
rs780_before_pci_init();
sb700_before_pci_init();
post_cache_as_ram();
}

59
src/mainboard/amd/mahogany/romstage.c
View File

@ -100,59 +100,9 @@ static inline int spd_read_byte(u32 device, u32 address)
#include "cpu/amd/model_fxx/fidvid.c"
#if CONFIG_USE_FALLBACK_IMAGE == 1
#include "northbridge/amd/amdk8/early_ht.c"
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
{
/* Is this a cpu only reset? Is this a secondary cpu? */
if ((cpu_init_detectedx) || (!boot_cpu())) {
if (last_boot_normal()) { /* RTC already inited */
goto normal_image;
} else {
goto fallback_image;
}
}
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* sb700_lpc_port80(); */
sb700_pci_port80();
/* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal()) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
goto normal_image;
} else {
goto fallback_image;
}
normal_image:
post_code(0x23);
__asm__ volatile ("jmp __normal_image": /* outputs */
:"a" (bist), "b"(cpu_init_detectedx) /* inputs */);
fallback_image:
post_code(0x25);
}
#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
#if CONFIG_USE_FALLBACK_IMAGE == 1
failover_process(bist, cpu_init_detectedx);
#endif
real_main(bist, cpu_init_detectedx);
}
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
int needs_reset = 0;
@ -161,6 +111,15 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
struct cpuid_result cpuid1;
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
if (!((cpu_init_detectedx) || (!boot_cpu()))) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* sb700_lpc_port80(); */
sb700_pci_port80();
}
if (bist == 0) {
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
}

59
src/mainboard/amd/pistachio/romstage.c
View File

@ -94,59 +94,9 @@ static inline int spd_read_byte(u32 device, u32 address)
#include "cpu/amd/model_fxx/fidvid.c"
#if CONFIG_USE_FALLBACK_IMAGE == 1
#include "northbridge/amd/amdk8/early_ht.c"
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
{
/* Is this a cpu only reset? Is this a secondary cpu? */
if ((cpu_init_detectedx) || (!boot_cpu())) {
if (last_boot_normal()) { /* RTC already inited */
goto normal_image;
} else {
goto fallback_image;
}
}
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
sb600_lpc_port80();
/* sb600_pci_port80(); */
/* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal()) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
goto normal_image;
} else {
goto fallback_image;
}
normal_image:
post_code(0x01);
__asm__ volatile ("jmp __normal_image": /* outputs */
:"a" (bist), "b"(cpu_init_detectedx)); /* inputs */
fallback_image:
post_code(0x02);
}
#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
#if CONFIG_USE_FALLBACK_IMAGE == 1
failover_process(bist, cpu_init_detectedx);
#endif
real_main(bist, cpu_init_detectedx);
}
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
int needs_reset = 0;
@ -157,6 +107,15 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
(struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE -
CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
if (!((cpu_init_detectedx) || (!boot_cpu()))) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
sb600_lpc_port80();
/* sb600_pci_port80(); */
}
if (bist == 0) {
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
}

64
src/mainboard/arima/hdama/romstage.c
View File

@ -95,65 +95,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/init_cpus.c"
#if CONFIG_USE_FALLBACK_IMAGE == 1
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
{
unsigned last_boot_normal_x = last_boot_normal();
/* Is this a cpu only reset? or Is this a secondary cpu? */
if ((cpu_init_detectedx) || (!boot_cpu())) {
if (last_boot_normal_x) {
goto normal_image;
} else {
goto fallback_image;
}
}
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
amd8111_enable_rom();
/* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal_x) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
__asm__ volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist) , "b" (cpu_init_detectedx) /* inputs */
);
fallback_image:
;
}
#endif
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
#if CONFIG_USE_FALLBACK_IMAGE == 1
failover_process(bist, cpu_init_detectedx);
#endif
real_main(bist, cpu_init_detectedx);
}
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
(0xa<<3)|0, (0xa<<3)|2, 0, 0,
@ -169,6 +114,15 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
struct mem_controller ctrl[8];
unsigned nodes;
if (!((cpu_init_detectedx) || (!boot_cpu()))) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
amd8111_enable_rom();
}
if (bist == 0) {
bsp_apicid = init_cpus(cpu_init_detectedx);
}

75
src/mainboard/asus/a8v-e_se/romstage.c
View File

@ -176,67 +176,7 @@ void sio_init(void)
pnp_exit_ext_func_mode(GPIO_DEV);
}
#if CONFIG_USE_FALLBACK_IMAGE == 1
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
{
/* unsigned last_boot_normal_x = last_boot_normal(); */
/* FIXME */
unsigned last_boot_normal_x = 1;
sio_init();
w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
enable_rom_decode();
print_info("now booting... fallback\r\n");
/* Is this a CPU only reset? Or is this a secondary CPU? */
if ((cpu_init_detectedx) || (!boot_cpu())) {
if (last_boot_normal_x)
goto normal_image;
else
goto fallback_image;
}
/* Nothing special needs to be done to find bus 0. */
/* Allow the HT devices to be found. */
enumerate_ht_chain();
/* Is this a deliberate reset by the BIOS? */
if (bios_reset_detected() && last_boot_normal_x) {
goto normal_image;
}
/* This is the primary CPU, how should I boot? */
else if (do_normal_boot()) {
goto normal_image;
} else {
goto fallback_image;
}
normal_image:
/* print_info("JMP normal image\r\n"); */
__asm__ __volatile__("jmp __normal_image":
:"a" (bist), "b" (cpu_init_detectedx));
fallback_image:
;
}
#endif
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
#if CONFIG_USE_FALLBACK_IMAGE == 1
failover_process(bist, cpu_init_detectedx);
#endif
real_main(bist, cpu_init_detectedx);
}
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
(0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
@ -258,6 +198,21 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
console_init();
enable_rom_decode();
print_info("now booting... fallback\r\n");
/* Is this a CPU only reset? Or is this a secondary CPU? */
if (!((cpu_init_detectedx) || (!boot_cpu()))) {
/* Nothing special needs to be done to find bus 0. */
/* Allow the HT devices to be found. */
enumerate_ht_chain();
}
sio_init();
w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
enable_rom_decode();
print_info("now booting... real_main\r\n");
if (bist == 0)

78
src/mainboard/broadcom/blast/romstage.c
View File

@ -106,73 +106,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/init_cpus.c"
#if CONFIG_USE_FALLBACK_IMAGE == 1
#include "northbridge/amd/amdk8/early_ht.c"
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
{
/* Is this a cpu only reset? Is this a secondary cpu? */
if ((cpu_init_detectedx) || (!boot_cpu())) {
if (last_boot_normal()) { // RTC already inited
goto normal_image;
} else {
goto fallback_image;
}
}
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
bcm5785_enable_rom();
bcm5785_enable_lpc();
//enable RTC
pc87417_enable_dev(RTC_DEV);
/* Is this a deliberate reset by the bios */
// post_code(0x22);
if (bios_reset_detected() && last_boot_normal()) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
// post_code(0x23);
__asm__ volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
);
fallback_image:
// post_code(0x25);
;
}
#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
#if CONFIG_USE_FALLBACK_IMAGE == 1
failover_process(bist, cpu_init_detectedx);
#endif
real_main(bist, cpu_init_detectedx);
}
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
RC0|DIMM0, RC0|DIMM2, 0, 0,
@ -189,6 +125,20 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
struct mem_controller ctrl[8];
unsigned nodes;
if (!((cpu_init_detectedx) || (!boot_cpu()))) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
bcm5785_enable_rom();
bcm5785_enable_lpc();
//enable RTC
pc87417_enable_dev(RTC_DEV);
}
if (bist == 0) {
bsp_apicid = init_cpus(cpu_init_detectedx);
}

30
src/mainboard/dell/s1850/failover.c
View File

@ -15,35 +15,5 @@
static unsigned long main(unsigned long bist)
{
/* skip all this nonsense as we are not doing fallback yet */
goto fallback_image;
/* Did just the cpu reset? */
if (memory_initialized()) {
if (last_boot_normal()) {
goto normal_image;
} else {
goto cpu_reset;
}
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
asm volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist) /* inputs */
: /* clobbers */
);
cpu_reset:
asm volatile ("jmp __cpu_reset"
: /* outputs */
: "a"(bist) /* inputs */
: /* clobbers */
);
fallback_image:
return bist;
}

15
src/mainboard/emulation/qemu-x86/failover.c
View File

@ -10,20 +10,5 @@
static void main(void)
{
#if 0
/* Is this a cpu reset? */
if (cpu_init_detected()) {
if (last_boot_normal()) {
asm("jmp __normal_image");
} else {
asm("jmp __cpu_reset");
}
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
asm("jmp __normal_image");
}
#endif
}

65
src/mainboard/ibm/e325/romstage.c
View File

@ -93,66 +93,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/init_cpus.c"
#if CONFIG_USE_FALLBACK_IMAGE == 1
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
{
unsigned last_boot_normal_x = last_boot_normal();
/* Is this a cpu only reset? or Is this a secondary cpu? */
if ((cpu_init_detectedx) || (!boot_cpu())) {
if (last_boot_normal_x) {
goto normal_image;
} else {
goto fallback_image;
}
}
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
amd8111_enable_rom();
/* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal_x) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
__asm__ volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist) , "b" (cpu_init_detectedx) /* inputs */
);
fallback_image:
;
}
#endif
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
#if CONFIG_USE_FALLBACK_IMAGE == 1
failover_process(bist, cpu_init_detectedx);
#endif
real_main(bist, cpu_init_detectedx);
}
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const struct mem_controller cpu[] = {
{
@ -179,6 +123,15 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
int needs_reset;
if (!((cpu_init_detectedx) || (!boot_cpu()))) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
amd8111_enable_rom();
}
if (bist == 0) {
init_cpus(cpu_init_detectedx);
}

66
src/mainboard/ibm/e326/romstage.c
View File

@ -92,67 +92,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/init_cpus.c"
#if CONFIG_USE_FALLBACK_IMAGE == 1
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
{
unsigned last_boot_normal_x = last_boot_normal();
/* Is this a cpu only reset? or Is this a secondary cpu? */
if ((cpu_init_detectedx) || (!boot_cpu())) {
if (last_boot_normal_x) {
goto normal_image;
} else {
goto fallback_image;
}
}
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
amd8111_enable_rom();
/* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal_x) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
__asm__ volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist) , "b" (cpu_init_detectedx) /* inputs */
);
fallback_image:
;
}
#endif
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
#if CONFIG_USE_FALLBACK_IMAGE == 1
failover_process(bist, cpu_init_detectedx);
#endif
real_main(bist, cpu_init_detectedx);
}
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const struct mem_controller cpu[] = {
{
@ -179,6 +122,15 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
int needs_reset;
if (!((cpu_init_detectedx) || (!boot_cpu()))) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
amd8111_enable_rom();
}
if (bist == 0) {
init_cpus(cpu_init_detectedx);
}

29
src/mainboard/intel/jarrell/failover.c
View File

@ -14,34 +14,5 @@
static unsigned long main(unsigned long bist)
{
/* Did just the cpu reset? */
if (memory_initialized()) {
if (last_boot_normal()) {
goto normal_image;
} else {
goto cpu_reset;
}
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
asm volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist) /* inputs */
: /* clobbers */
);
cpu_reset:
asm volatile ("jmp __cpu_reset"
: /* outputs */
: "a"(bist) /* inputs */
: /* clobbers */
);
fallback_image:
return bist;
}

31
src/mainboard/intel/xe7501devkit/failover.c
View File

@ -13,36 +13,5 @@
static unsigned long main(unsigned long bist)
{
/* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal()) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else {
check_cmos_failed();
if (do_normal_boot()) {
goto normal_image;
}
else {
goto fallback_image;
}
}
normal_image:
asm volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist) /* inputs */
: /* clobbers */
);
#if 0
cpu_reset:
asm volatile ("jmp __cpu_reset"
: /* outputs */
: "a"(bist) /* inputs */
: /* clobbers */
);
#endif
fallback_image:
return bist;
}

58
src/mainboard/kontron/kt690/romstage.c
View File

@ -101,59 +101,9 @@ static inline int spd_read_byte(u32 device, u32 address)
#include "cpu/amd/model_fxx/fidvid.c"
#if CONFIG_USE_FALLBACK_IMAGE == 1
#include "northbridge/amd/amdk8/early_ht.c"
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
{
/* Is this a cpu only reset? Is this a secondary cpu? */
if ((cpu_init_detectedx) || (!boot_cpu())) {
if (last_boot_normal()) { /* RTC already inited */
goto normal_image;
} else {
goto fallback_image;
}
}
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* sb600_lpc_port80(); */
sb600_pci_port80();
/* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal()) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
goto normal_image;
} else {
goto fallback_image;
}
normal_image:
post_code(0x23);
__asm__ volatile ("jmp __normal_image": /* outputs */
:"a" (bist), "b"(cpu_init_detectedx) /* inputs */);
fallback_image:
post_code(0x25);
}
#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
#if CONFIG_USE_FALLBACK_IMAGE == 1
failover_process(bist, cpu_init_detectedx);
#endif
real_main(bist, cpu_init_detectedx);
}
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
device_t dev;
static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
@ -163,6 +113,14 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
struct cpuid_result cpuid1;
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
if (!((cpu_init_detectedx) || (!boot_cpu()))) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* sb600_lpc_port80(); */
sb600_pci_port80();
}
if (bist == 0) {
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);

77
src/mainboard/msi/ms9185/romstage.c
View File

@ -153,72 +153,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/fidvid.c"
#if CONFIG_USE_FALLBACK_IMAGE == 1
#include "northbridge/amd/amdk8/early_ht.c"
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
{
/* Is this a cpu only reset? Is this a secondary cpu? */
if ((cpu_init_detectedx) || (!boot_cpu())) {
if (last_boot_normal()) { // RTC already inited
goto normal_image;
} else {
goto fallback_image;
}
}
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
bcm5785_enable_rom();
bcm5785_enable_lpc();
//enable RTC
pc87417_enable_dev(RTC_DEV);
/* Is this a deliberate reset by the bios */
// post_code(0x22);
if (bios_reset_detected() && last_boot_normal()) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
// post_code(0x23);
__asm__ volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
);
fallback_image:
// post_code(0x25);
;
}
#endif
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
#if CONFIG_USE_FALLBACK_IMAGE == 1
failover_process(bist, cpu_init_detectedx);
#endif
real_main(bist, cpu_init_detectedx);
}
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
//first node
@ -237,6 +174,20 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
int needs_reset;
unsigned bsp_apicid = 0;
if (!((cpu_init_detectedx) || (!boot_cpu()))) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
bcm5785_enable_rom();
bcm5785_enable_lpc();
//enable RTC
pc87417_enable_dev(RTC_DEV);
}
if (bist == 0) {
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
}

72
src/mainboard/msi/ms9282/romstage.c
View File

@ -133,8 +133,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/init_cpus.c"
#include "cpu/amd/model_fxx/fidvid.c"
#if CONFIG_USE_FALLBACK_IMAGE == 1
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
@ -155,69 +153,13 @@ static void sio_setup(void)
pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
}
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
{
unsigned last_boot_normal_x = last_boot_normal();
/* Is this a cpu only reset? or Is this a secondary cpu? */
if ((cpu_init_detectedx) || (!boot_cpu())) {
if (last_boot_normal_x) {
goto normal_image;
} else {
goto fallback_image;
}
}
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
sio_setup();
/* Setup the mcp55 */
mcp55_enable_rom();
/* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal_x) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
__asm__ volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist), "b"(cpu_init_detectedx) /* inputs */
);
fallback_image:
;
}
#endif
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
#if CONFIG_USE_FALLBACK_IMAGE == 1
failover_process(bist, cpu_init_detectedx);
#endif
real_main(bist, cpu_init_detectedx);
}
//CPU 1 mem is on SMBUS_HUB channel 2, and CPU 2 mem is on channel 1.
#define RC0 (2<<8)
#define RC1 (1<<8)
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
RC0|(0xa<<3)|0, RC0|(0xa<<3)|2, RC0|(0xa<<3)|4, RC0|(0xa<<3)|6,
@ -233,6 +175,18 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
char *p ;
if (!((cpu_init_detectedx) || (!boot_cpu()))) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
sio_setup();
/* Setup the mcp55 */
mcp55_enable_rom();
}
if (bist == 0) {
//init_cpus(cpu_init_detectedx);
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);

70
src/mainboard/newisys/khepri/romstage.c
View File

@ -108,70 +108,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/init_cpus.c"
#if CONFIG_USE_FALLBACK_IMAGE == 1
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
{
unsigned last_boot_normal_x = last_boot_normal();
/* Is this a cpu only reset? or Is this a secondary cpu? */
if ((cpu_init_detectedx) || (!boot_cpu())) {
if (last_boot_normal_x) {
goto normal_image;
} else {
goto fallback_image;
}
}
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* Setup the amd8111 */
amd8111_enable_rom();
/* Is this a deliberate reset by the bios */
// post_code(0x22);
if (bios_reset_detected() && last_boot_normal_x) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
// post_code(0x23);
__asm__ volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
);
fallback_image:
// post_code(0x25);
;
}
#endif
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
#if CONFIG_USE_FALLBACK_IMAGE == 1
failover_process(bist, cpu_init_detectedx);
#endif
real_main(bist, cpu_init_detectedx);
}
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
(0xa<<3)|0, (0xa<<3)|2, 0, 0,
@ -188,6 +128,16 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
struct mem_controller ctrl[8];
unsigned nodes;
if (!((cpu_init_detectedx) || (!boot_cpu()))) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* Setup the amd8111 */
amd8111_enable_rom();
}
if (bist == 0) {
bsp_apicid = init_cpus(cpu_init_detectedx);
}

22
src/mainboard/olpc/btest/failover.c
View File

@ -9,27 +9,5 @@
static unsigned long main(unsigned long bist)
{
#if 0
/* This is the primary cpu how should I boot? */
if (do_normal_boot()) {
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
asm volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist) /* inputs */
: /* clobbers */
);
cpu_reset:
asm volatile ("jmp __cpu_reset"
: /* outputs */
: "a"(bist) /* inputs */
: /* clobbers */
);
fallback_image:
#endif
return bist;
}

22
src/mainboard/olpc/rev_a/failover.c
View File

@ -9,27 +9,5 @@
static unsigned long main(unsigned long bist)
{
#if 0
/* This is the primary cpu how should I boot? */
if (do_normal_boot()) {
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
asm volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist) /* inputs */
: /* clobbers */
);
cpu_reset:
asm volatile ("jmp __cpu_reset"
: /* outputs */
: "a"(bist) /* inputs */
: /* clobbers */
);
fallback_image:
#endif
return bist;
}

71
src/mainboard/sunw/ultra40/romstage.c
View File

@ -112,8 +112,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/init_cpus.c"
#if CONFIG_USE_FALLBACK_IMAGE == 1
#include "southbridge/nvidia/ck804/ck804_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
@ -146,64 +144,7 @@ static void sio_setup(void)
}
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
{
unsigned last_boot_normal_x = last_boot_normal();
/* Is this a cpu only reset? or Is this a secondary cpu? */
if ((cpu_init_detectedx) || (!boot_cpu())) {
if (last_boot_normal_x) {
goto normal_image;
} else {
goto fallback_image;
}
}
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
sio_setup();
/* Setup the ck804 */
ck804_enable_rom();
/* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal_x) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
__asm__ volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
);
fallback_image:
;
}
#endif
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
#if CONFIG_USE_FALLBACK_IMAGE == 1
failover_process(bist, cpu_init_detectedx);
#endif
real_main(bist, cpu_init_detectedx);
}
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
(0xa<<3)|0, (0xa<<3)|2, 0, 0,
@ -220,6 +161,18 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
struct mem_controller ctrl[8];
unsigned nodes;
if (!((cpu_init_detectedx) || (!boot_cpu()))) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
sio_setup();
/* Setup the ck804 */
ck804_enable_rom();
}
if (bist == 0) {
bsp_apicid = init_cpus(cpu_init_detectedx);
}

29
src/mainboard/supermicro/x6dai_g/failover.c
View File

@ -14,34 +14,5 @@
static unsigned long main(unsigned long bist)
{
/* Did just the cpu reset? */
if (memory_initialized()) {
if (last_boot_normal()) {
goto normal_image;
} else {
goto cpu_reset;
}
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
asm volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist) /* inputs */
: /* clobbers */
);
cpu_reset:
asm volatile ("jmp __cpu_reset"
: /* outputs */
: "a"(bist) /* inputs */
: /* clobbers */
);
fallback_image:
return bist;
}

29
src/mainboard/supermicro/x6dhe_g/failover.c
View File

@ -14,34 +14,5 @@
static unsigned long main(unsigned long bist)
{
/* Did just the cpu reset? */
if (memory_initialized()) {
if (last_boot_normal()) {
goto normal_image;
} else {
goto cpu_reset;
}
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
asm volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist) /* inputs */
: /* clobbers */
);
cpu_reset:
asm volatile ("jmp __cpu_reset"
: /* outputs */
: "a"(bist) /* inputs */
: /* clobbers */
);
fallback_image:
return bist;
}

29
src/mainboard/supermicro/x6dhe_g2/failover.c
View File

@ -14,34 +14,5 @@
static unsigned long main(unsigned long bist)
{
/* Did just the cpu reset? */
if (memory_initialized()) {
if (last_boot_normal()) {
goto normal_image;
} else {
goto cpu_reset;
}
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
asm volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist) /* inputs */
: /* clobbers */
);
cpu_reset:
asm volatile ("jmp __cpu_reset"
: /* outputs */
: "a"(bist) /* inputs */
: /* clobbers */
);
fallback_image:
return bist;
}

29
src/mainboard/supermicro/x6dhr_ig/failover.c
View File

@ -14,34 +14,5 @@
static unsigned long main(unsigned long bist)
{
/* Did just the cpu reset? */
if (memory_initialized()) {
if (last_boot_normal()) {
goto normal_image;
} else {
goto cpu_reset;
}
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
asm volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist) /* inputs */
: /* clobbers */
);
cpu_reset:
asm volatile ("jmp __cpu_reset"
: /* outputs */
: "a"(bist) /* inputs */
: /* clobbers */
);
fallback_image:
return bist;
}

29
src/mainboard/supermicro/x6dhr_ig2/failover.c
View File

@ -14,34 +14,5 @@
static unsigned long main(unsigned long bist)
{
/* Did just the cpu reset? */
if (memory_initialized()) {
if (last_boot_normal()) {
goto normal_image;
} else {
goto cpu_reset;
}
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
asm volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist) /* inputs */
: /* clobbers */
);
cpu_reset:
asm volatile ("jmp __cpu_reset"
: /* outputs */
: "a"(bist) /* inputs */
: /* clobbers */
);
fallback_image:
return bist;
}

60
src/mainboard/technexion/tim5690/romstage.c
View File

@ -103,60 +103,9 @@ static inline int spd_read_byte(u32 device, u32 address)
#include "tn_post_code.c"
#include "speaker.c"
#if CONFIG_USE_FALLBACK_IMAGE == 1
#include "northbridge/amd/amdk8/early_ht.c"
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
{
/* Is this a cpu only reset? Is this a secondary cpu? */
if ((cpu_init_detectedx) || (!boot_cpu())) {
if (last_boot_normal()) { /* RTC already inited */
goto normal_image;
} else {
goto fallback_image;
}
}
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* sb600_lpc_port80(); */
sb600_pci_port80();
/* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal()) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
goto normal_image;
} else {
goto fallback_image;
}
normal_image:
post_code(0x23);
__asm__ volatile ("jmp __normal_image": /* outputs */
:"a" (bist), "b"(cpu_init_detectedx) /* inputs */);
fallback_image:
post_code(0x25);
}
#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
#if CONFIG_USE_FALLBACK_IMAGE == 1
failover_process(bist, cpu_init_detectedx);
#endif
real_main(bist, cpu_init_detectedx);
}
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
int needs_reset = 0;
@ -165,6 +114,15 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
struct cpuid_result cpuid1;
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
if (!((cpu_init_detectedx) || (!boot_cpu()))) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* sb600_lpc_port80(); */
sb600_pci_port80();
}
technexion_post_code_init();
technexion_post_code(LED_MESSAGE_START);

59
src/mainboard/technexion/tim8690/romstage.c
View File

@ -100,59 +100,9 @@ static inline int spd_read_byte(u32 device, u32 address)
#include "cpu/amd/model_fxx/fidvid.c"
#if CONFIG_USE_FALLBACK_IMAGE == 1
#include "northbridge/amd/amdk8/early_ht.c"
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
{
/* Is this a cpu only reset? Is this a secondary cpu? */
if ((cpu_init_detectedx) || (!boot_cpu())) {
if (last_boot_normal()) { /* RTC already inited */
goto normal_image;
} else {
goto fallback_image;
}
}
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* sb600_lpc_port80(); */
sb600_pci_port80();
/* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal()) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
goto normal_image;
} else {
goto fallback_image;
}
normal_image:
post_code(0x23);
__asm__ volatile ("jmp __normal_image": /* outputs */
:"a" (bist), "b"(cpu_init_detectedx) /* inputs */);
fallback_image:
post_code(0x25);
}
#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
#if CONFIG_USE_FALLBACK_IMAGE == 1
failover_process(bist, cpu_init_detectedx);
#endif
real_main(bist, cpu_init_detectedx);
}
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
int needs_reset = 0;
@ -162,6 +112,15 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
if (!((cpu_init_detectedx) || (!boot_cpu()))) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* sb600_lpc_port80(); */
sb600_pci_port80();
}
if (bist == 0) {
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
}

46
src/mainboard/tyan/s2735/romstage.c
View File

@ -80,53 +80,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/x86/car/copy_and_run.c"
#if CONFIG_USE_FALLBACK_IMAGE == 1
#include "southbridge/intel/i82801ex/cmos_failover.c"
void real_main(unsigned long bist);
void amd64_main(unsigned long bist)
{
/* Is this a deliberate reset by the bios */
// post_code(0x22);
if (bios_reset_detected() && last_boot_normal()) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else {
check_cmos_failed();
if (do_normal_boot()) {
goto normal_image;
}
else {
goto fallback_image;
}
}
normal_image:
// post_code(0x23);
__asm__ volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist) /* inputs */
);
cpu_reset:
// post_code(0x24);
#if 0
//CPU reset will reset memtroller ???
asm volatile ("jmp __cpu_reset"
: /* outputs */
: "a"(bist) /* inputs */
);
#endif
fallback_image:
// post_code(0x25);
real_main(bist);
}
void real_main(unsigned long bist)
#else
void amd64_main(unsigned long bist)
#endif
{
static const struct mem_controller memctrl[] = {
{

71
src/mainboard/tyan/s2850/romstage.c
View File

@ -93,71 +93,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/init_cpus.c"
#if CONFIG_USE_FALLBACK_IMAGE == 1
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
{
unsigned last_boot_normal_x = last_boot_normal();
/* Is this a cpu only reset? or Is this a secondary cpu? */
if ((cpu_init_detectedx) || (!boot_cpu())) {
if (last_boot_normal_x) {
goto normal_image;
} else {
goto fallback_image;
}
}
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* Setup the amd8111 */
amd8111_enable_rom();
/* Is this a deliberate reset by the bios */
// post_code(0x22);
if (bios_reset_detected() && last_boot_normal_x) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
// post_code(0x23);
__asm__ volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
);
fallback_image:
// post_code(0x25);
;
}
#endif
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
#if CONFIG_USE_FALLBACK_IMAGE == 1
failover_process(bist, cpu_init_detectedx);
#endif
real_main(bist, cpu_init_detectedx);
}
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const struct mem_controller cpu[] = {
{
@ -173,6 +112,16 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
int needs_reset;
if (!((cpu_init_detectedx) || (!boot_cpu()))) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* Setup the amd8111 */
amd8111_enable_rom();
}
if (bist == 0) {
init_cpus(cpu_init_detectedx);
}

67
src/mainboard/tyan/s2875/romstage.c
View File

@ -84,68 +84,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/init_cpus.c"
#if CONFIG_USE_FALLBACK_IMAGE == 1
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
{
unsigned last_boot_normal_x = last_boot_normal();
/* Is this a cpu only reset? or Is this a secondary cpu? */
if ((cpu_init_detectedx) || (!boot_cpu())) {
if (last_boot_normal_x) {
goto normal_image;
} else {
goto fallback_image;
}
}
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
amd8111_enable_rom();
/* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal_x) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
__asm__ volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist), "b" (cpu_init_detectedx)/* inputs */
);
fallback_image:
;
}
#endif
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
#if CONFIG_USE_FALLBACK_IMAGE == 1
failover_process(bist, cpu_init_detectedx);
#endif
real_main(bist, cpu_init_detectedx);
}
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const struct mem_controller cpu[] = {
{
@ -172,6 +114,15 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
int needs_reset;
if (!((cpu_init_detectedx) || (!boot_cpu()))) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
amd8111_enable_rom();
}
if (bist == 0) {
init_cpus(cpu_init_detectedx);
}

66
src/mainboard/tyan/s2880/romstage.c
View File

@ -85,67 +85,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/init_cpus.c"
#if CONFIG_USE_FALLBACK_IMAGE == 1
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
{
unsigned last_boot_normal_x = last_boot_normal();
/* Is this a cpu only reset? or Is this a secondary cpu? */
if ((cpu_init_detectedx) || (!boot_cpu())) {
if (last_boot_normal_x) {
goto normal_image;
} else {
goto fallback_image;
}
}
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
amd8111_enable_rom();
/* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal_x) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
__asm__ volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
);
fallback_image:
;
}
#endif
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
#if CONFIG_USE_FALLBACK_IMAGE == 1
failover_process(bist, cpu_init_detectedx);
#endif
real_main(bist, cpu_init_detectedx);
}
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const struct mem_controller cpu[] = {
{
@ -172,6 +115,15 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
int needs_reset;
if (!((cpu_init_detectedx) || (!boot_cpu()))) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
amd8111_enable_rom();
}
if (bist == 0) {
init_cpus(cpu_init_detectedx);
}

71
src/mainboard/tyan/s2881/romstage.c
View File

@ -98,71 +98,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/init_cpus.c"
#if CONFIG_USE_FALLBACK_IMAGE == 1
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
{
unsigned last_boot_normal_x = last_boot_normal();
/* Is this a cpu only reset? or Is this a secondary cpu? */
if ((cpu_init_detectedx) || (!boot_cpu())) {
if (last_boot_normal_x) {
goto normal_image;
} else {
goto fallback_image;
}
}
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* Setup the amd8111 */
amd8111_enable_rom();
/* Is this a deliberate reset by the bios */
// post_code(0x22);
if (bios_reset_detected() && last_boot_normal_x) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
// post_code(0x23);
__asm__ volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
);
fallback_image:
// post_code(0x25);
;
}
#endif
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
#if CONFIG_USE_FALLBACK_IMAGE == 1
failover_process(bist, cpu_init_detectedx);
#endif
real_main(bist, cpu_init_detectedx);
}
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
(0xa<<3)|0, (0xa<<3)|2, 0, 0,
@ -179,6 +118,16 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
struct mem_controller ctrl[8];
unsigned nodes;
if (!((cpu_init_detectedx) || (!boot_cpu()))) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* Setup the amd8111 */
amd8111_enable_rom();
}
if (bist == 0) {
bsp_apicid = init_cpus(cpu_init_detectedx);
}

66
src/mainboard/tyan/s2882/romstage.c
View File

@ -88,67 +88,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/init_cpus.c"
#if CONFIG_USE_FALLBACK_IMAGE == 1
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
{
unsigned last_boot_normal_x = last_boot_normal();
/* Is this a cpu only reset? or Is this a secondary cpu? */
if ((cpu_init_detectedx) || (!boot_cpu())) {
if (last_boot_normal_x) {
goto normal_image;
} else {
goto fallback_image;
}
}
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
amd8111_enable_rom();
/* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal_x) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
__asm__ volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist) , "b" (cpu_init_detectedx) /* inputs */
);
fallback_image:
;
}
#endif
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
#if CONFIG_USE_FALLBACK_IMAGE == 1
failover_process(bist, cpu_init_detectedx);
#endif
real_main(bist, cpu_init_detectedx);
}
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const struct mem_controller cpu[] = {
{
@ -175,6 +118,15 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
int needs_reset;
if (!((cpu_init_detectedx) || (!boot_cpu()))) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
amd8111_enable_rom();
}
if (bist == 0) {
init_cpus(cpu_init_detectedx);
}

71
src/mainboard/tyan/s2885/romstage.c
View File

@ -98,71 +98,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/init_cpus.c"
#if CONFIG_USE_FALLBACK_IMAGE == 1
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
{
unsigned last_boot_normal_x = last_boot_normal();
/* Is this a cpu only reset? or Is this a secondary cpu? */
if ((cpu_init_detectedx) || (!boot_cpu())) {
if (last_boot_normal_x) {
goto normal_image;
} else {
goto fallback_image;
}
}
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* Setup the amd8111 */
amd8111_enable_rom();
/* Is this a deliberate reset by the bios */
// post_code(0x22);
if (bios_reset_detected() && last_boot_normal_x) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
// post_code(0x23);
__asm__ volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
);
fallback_image:
// post_code(0x25);
;
}
#endif
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
#if CONFIG_USE_FALLBACK_IMAGE == 1
failover_process(bist, cpu_init_detectedx);
#endif
real_main(bist, cpu_init_detectedx);
}
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
(0xa<<3)|0, (0xa<<3)|2, 0, 0,
@ -179,6 +118,16 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
struct mem_controller ctrl[8];
unsigned nodes;
if (!((cpu_init_detectedx) || (!boot_cpu()))) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* Setup the amd8111 */
amd8111_enable_rom();
}
if (bist == 0) {
bsp_apicid = init_cpus(cpu_init_detectedx);
}

74
src/mainboard/tyan/s2891/romstage.c
View File

@ -77,8 +77,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/init_cpus.c"
#if CONFIG_USE_FALLBACK_IMAGE == 1
#include "southbridge/nvidia/ck804/ck804_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
@ -112,67 +110,7 @@ static void sio_setup(void)
}
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
{
unsigned last_boot_normal_x = last_boot_normal();
/* Is this a cpu only reset? or Is this a secondary cpu? */
if ((cpu_init_detectedx) || (!boot_cpu())) {
if (last_boot_normal_x) {
goto normal_image;
} else {
goto fallback_image;
}
}
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
sio_setup();
/* Setup the ck804 */
ck804_enable_rom();
/* Is this a deliberate reset by the bios */
// post_code(0x22);
if (bios_reset_detected() && last_boot_normal_x) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
// post_code(0x23);
__asm__ volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist), "b"(cpu_init_detectedx) /* inputs */
);
fallback_image:
// post_code(0x25);
;
}
#endif
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
#if CONFIG_USE_FALLBACK_IMAGE == 1
failover_process(bist, cpu_init_detectedx);
#endif
real_main(bist, cpu_init_detectedx);
}
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
(0xa<<3)|0, (0xa<<3)|2, 0, 0,
@ -189,6 +127,18 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
struct mem_controller ctrl[8];
unsigned nodes;
if (!((cpu_init_detectedx) || (!boot_cpu()))) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
sio_setup();
/* Setup the ck804 */
ck804_enable_rom();
}
if (bist == 0) {
bsp_apicid = init_cpus(cpu_init_detectedx);
}

72
src/mainboard/tyan/s2892/romstage.c
View File

@ -82,8 +82,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/init_cpus.c"
#if CONFIG_USE_FALLBACK_IMAGE == 1
#include "southbridge/nvidia/ck804/ck804_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
@ -101,65 +99,7 @@ static void sio_setup(void)
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
}
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
{
unsigned last_boot_normal_x = last_boot_normal();
/* Is this a cpu only reset? or Is this a secondary cpu? */
if ((cpu_init_detectedx) || (!boot_cpu())) {
if (last_boot_normal_x) {
goto normal_image;
} else {
goto fallback_image;
}
}
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
sio_setup();
/* Setup the ck804 */
ck804_enable_rom();
/* Is this a deliberate reset by the bios */
// post_code(0x22);
if (bios_reset_detected() && last_boot_normal_x) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
// post_code(0x23);
__asm__ volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist), "b"(cpu_init_detectedx) /* inputs */
);
fallback_image:
// post_code(0x25);
;
}
#endif
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
#if CONFIG_USE_FALLBACK_IMAGE == 1
failover_process(bist, cpu_init_detectedx);
#endif
real_main(bist, cpu_init_detectedx);
}
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
(0xa<<3)|0, (0xa<<3)|2, 0, 0,
@ -176,6 +116,18 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
struct mem_controller ctrl[8];
unsigned nodes;
if (!((cpu_init_detectedx) || (!boot_cpu()))) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
sio_setup();
/* Setup the ck804 */
ck804_enable_rom();
}
if (bist == 0) {
bsp_apicid = init_cpus(cpu_init_detectedx);
}

66
src/mainboard/tyan/s4880/romstage.c
View File

@ -111,67 +111,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/init_cpus.c"
#if CONFIG_USE_FALLBACK_IMAGE == 1
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
{
unsigned last_boot_normal_x = last_boot_normal();
/* Is this a cpu only reset? or Is this a secondary cpu? */
if ((cpu_init_detectedx) || (!boot_cpu())) {
if (last_boot_normal_x) {
goto normal_image;
} else {
goto fallback_image;
}
}
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
amd8111_enable_rom();
/* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal_x) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
__asm__ volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
);
fallback_image:
;
}
#endif
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
#if CONFIG_USE_FALLBACK_IMAGE == 1
failover_process(bist, cpu_init_detectedx);
#endif
real_main(bist, cpu_init_detectedx);
}
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const struct mem_controller cpu[] = {
{
@ -222,6 +165,15 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
int needs_reset;
if (!((cpu_init_detectedx) || (!boot_cpu()))) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
amd8111_enable_rom();
}
if (bist == 0) {
init_cpus(cpu_init_detectedx);
}

65
src/mainboard/tyan/s4882/romstage.c
View File

@ -119,66 +119,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/init_cpus.c"
#if CONFIG_USE_FALLBACK_IMAGE == 1
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
{
unsigned last_boot_normal_x = last_boot_normal();
/* Is this a cpu only reset? or Is this a secondary cpu? */
if ((cpu_init_detectedx) || (!boot_cpu())) {
if (last_boot_normal_x) {
goto normal_image;
} else {
goto fallback_image;
}
}
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
amd8111_enable_rom();
/* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal_x) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
__asm__ volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist), "b" ( cpu_init_detectedx ) /* inputs */
);
fallback_image:
;
}
#endif
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
#if CONFIG_USE_FALLBACK_IMAGE == 1
failover_process(bist, cpu_init_detectedx);
#endif
real_main(bist, cpu_init_detectedx);
}
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
RC0|DIMM0, RC0|DIMM2, 0, 0,
@ -201,6 +145,15 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
struct mem_controller ctrl[8];
unsigned nodes;
if (!((cpu_init_detectedx) || (!boot_cpu()))) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
amd8111_enable_rom();
}
if (bist == 0) {
bsp_apicid = init_cpus(cpu_init_detectedx);
}

22
src/mainboard/via/epia-m/failover.c
View File

@ -9,27 +9,5 @@
static unsigned long main(unsigned long bist)
{
#if 0
/* This is the primary cpu how should I boot? */
if (do_normal_boot()) {
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
asm volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist) /* inputs */
: /* clobbers */
);
cpu_reset:
asm volatile ("jmp __cpu_reset"
: /* outputs */
: "a"(bist) /* inputs */
: /* clobbers */
);
fallback_image:
#endif
return bist;
}

22
src/mainboard/via/epia-n/failover.c
View File

@ -9,27 +9,5 @@
static unsigned long main(unsigned long bist)
{
#if 0
/* This is the primary cpu how should I boot? */
if (do_normal_boot()) {
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
asm volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist) /* inputs */
: /* clobbers */
);
cpu_reset:
asm volatile ("jmp __cpu_reset"
: /* outputs */
: "a"(bist) /* inputs */
: /* clobbers */
);
fallback_image:
#endif
return bist;
}