soc/intel/spi: Move BIOS flash SPI controllers to fast SPI driver

There are two classes of SPI controllers on Intel chipsets:
 * generic usable SPI controllers
 * SPI controller hosting the BIOS flash (fast SPI controller)

While the first class can be used for generic peripheral attachment the
second class mostly controls the BIOS flash and a TPM device (if
enabled). The generic SPI driver is not fully applicable to the fast SPI
controller. In addition, the fast SPI controller reports the reserved
MMIO range used for the BIOS flash mapping so that the OS is aware of
this range.

This patch moves the fast SPI controller of all known SoCs to the
fast SPI driver in common code. In addition, the PCI device for the
fast SPI controller is removed from the function 'spi_soc_devfn_to_bus'
as this is a callback of the generic SPI driver.

Change-Id: Ia881c1d274acdcf7f042dd8284048a7dd018a84b
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

src/soc/intel/alderlake/spi.c

@@ -15,8 +15,6 @@
 int spi_soc_devfn_to_bus(unsigned int devfn)
 {
 	switch (devfn) {
-	case PCH_DEVFN_SPI:
-		return 0;
 	case PCH_DEVFN_GSPI0:
 		return 1;
 	case PCH_DEVFN_GSPI1:

src/soc/intel/cannonlake/spi.c

@@ -6,8 +6,6 @@
 int spi_soc_devfn_to_bus(unsigned int devfn)
 {
 	switch (devfn) {
-	case PCH_DEVFN_SPI:
-		return 0;
 	case PCH_DEVFN_GSPI0:
 		return 1;
 	case PCH_DEVFN_GSPI1:

src/soc/intel/common/block/fast_spi/fast_spi.c

@@ -541,8 +541,23 @@ static struct device_operations fast_spi_dev_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_ADP_M_N_HWSEQ_SPI,
+	PCI_DID_INTEL_ADP_P_HWSEQ_SPI,
+	PCI_DID_INTEL_ADP_S_HWSEQ_SPI,
 	PCI_DID_INTEL_APL_HWSEQ_SPI,
 	PCI_DID_INTEL_GLK_HWSEQ_SPI,
+	PCI_DID_INTEL_CMP_HWSEQ_SPI,
+	PCI_DID_INTEL_CMP_H_HWSEQ_SPI,
+	PCI_DID_INTEL_CNL_HWSEQ_SPI,
+	PCI_DID_INTEL_CNP_H_HWSEQ_SPI,
+	PCI_DID_INTEL_ICP_HWSEQ_SPI,
+	PCI_DID_INTEL_JSP_HWSEQ_SPI,
+	PCI_DID_INTEL_LWB_SPI,
+	PCI_DID_INTEL_LWB_SPI_SUPER,
+	PCI_DID_INTEL_MCC_SPI0,
+	PCI_DID_INTEL_MTL_HWSEQ_SPI,
+	PCI_DID_INTEL_SPR_HWSEQ_SPI,
+	PCI_DID_INTEL_TGP_SPI0,
 	0
 };
 

src/soc/intel/common/block/spi/spi.c

@@ -120,7 +120,6 @@ struct device_operations spi_dev_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
-	PCI_DID_INTEL_MTL_HWSEQ_SPI,
 	PCI_DID_INTEL_MTL_GSPI0,
 	PCI_DID_INTEL_MTL_GSPI1,
 	PCI_DID_INTEL_MTL_GSPI2,
@@ -133,26 +132,18 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_CNL_SPI0,
 	PCI_DID_INTEL_CNL_SPI1,
 	PCI_DID_INTEL_CNL_SPI2,
-	PCI_DID_INTEL_CNL_HWSEQ_SPI,
 	PCI_DID_INTEL_CNP_H_SPI0,
 	PCI_DID_INTEL_CNP_H_SPI1,
 	PCI_DID_INTEL_CNP_H_SPI2,
-	PCI_DID_INTEL_CNP_H_HWSEQ_SPI,
-	PCI_DID_INTEL_LWB_SPI,
-	PCI_DID_INTEL_LWB_SPI_SUPER,
 	PCI_DID_INTEL_ICP_SPI0,
 	PCI_DID_INTEL_ICP_SPI1,
 	PCI_DID_INTEL_ICP_SPI2,
-	PCI_DID_INTEL_ICP_HWSEQ_SPI,
 	PCI_DID_INTEL_CMP_SPI0,
 	PCI_DID_INTEL_CMP_SPI1,
 	PCI_DID_INTEL_CMP_SPI2,
-	PCI_DID_INTEL_CMP_HWSEQ_SPI,
 	PCI_DID_INTEL_CMP_H_SPI0,
 	PCI_DID_INTEL_CMP_H_SPI1,
 	PCI_DID_INTEL_CMP_H_SPI2,
-	PCI_DID_INTEL_CMP_H_HWSEQ_SPI,
-	PCI_DID_INTEL_TGP_SPI0,
 	PCI_DID_INTEL_TGP_GSPI0,
 	PCI_DID_INTEL_TGP_GSPI1,
 	PCI_DID_INTEL_TGP_GSPI2,
@@ -165,17 +156,12 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_TGP_H_GSPI1,
 	PCI_DID_INTEL_TGP_H_GSPI2,
 	PCI_DID_INTEL_TGP_H_GSPI3,
-	PCI_DID_INTEL_MCC_SPI0,
 	PCI_DID_INTEL_MCC_GSPI0,
 	PCI_DID_INTEL_MCC_GSPI1,
 	PCI_DID_INTEL_MCC_GSPI2,
 	PCI_DID_INTEL_JSP_SPI0,
 	PCI_DID_INTEL_JSP_SPI1,
 	PCI_DID_INTEL_JSP_SPI2,
-	PCI_DID_INTEL_JSP_HWSEQ_SPI,
-	PCI_DID_INTEL_ADP_P_HWSEQ_SPI,
-	PCI_DID_INTEL_ADP_S_HWSEQ_SPI,
-	PCI_DID_INTEL_ADP_M_N_HWSEQ_SPI,
 	PCI_DID_INTEL_ADP_P_SPI0,
 	PCI_DID_INTEL_ADP_P_SPI1,
 	PCI_DID_INTEL_ADP_P_SPI2,
@@ -193,7 +179,6 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_ADP_M_N_SPI0,
 	PCI_DID_INTEL_ADP_M_N_SPI1,
 	PCI_DID_INTEL_ADP_M_SPI2,
-	PCI_DID_INTEL_SPR_HWSEQ_SPI,
 	PCI_DID_INTEL_DNV_SPI,
 	0
 };

src/soc/intel/elkhartlake/spi.c

@@ -6,8 +6,6 @@
 int spi_soc_devfn_to_bus(unsigned int devfn)
 {
 	switch (devfn) {
-	case PCH_DEVFN_SPI:
-		return 0;
 	case PCH_DEVFN_GSPI0:
 		return 1;
 	case PCH_DEVFN_GSPI1:

src/soc/intel/icelake/spi.c

@@ -6,8 +6,6 @@
 int spi_soc_devfn_to_bus(unsigned int devfn)
 {
 	switch (devfn) {
-	case PCH_DEVFN_SPI:
-		return 0;
 	case PCH_DEVFN_GSPI0:
 		return 1;
 	case PCH_DEVFN_GSPI1:

src/soc/intel/jasperlake/spi.c

@@ -6,8 +6,6 @@
 int spi_soc_devfn_to_bus(unsigned int devfn)
 {
 	switch (devfn) {
-	case PCH_DEVFN_SPI:
-		return 0;
 	case PCH_DEVFN_GSPI0:
 		return 1;
 	case PCH_DEVFN_GSPI1:

src/soc/intel/meteorlake/spi.c

@@ -9,8 +9,6 @@
 int spi_soc_devfn_to_bus(unsigned int devfn)
 {
 	switch (devfn) {
-	case PCI_DEVFN_SPI:
-		return 0;
 	case PCI_DEVFN_GSPI0:
 		return 1;
 	case PCI_DEVFN_GSPI1:

src/soc/intel/skylake/spi.c

@@ -6,8 +6,6 @@
 int spi_soc_devfn_to_bus(unsigned int devfn)
 {
 	switch (devfn) {
-	case PCH_DEVFN_SPI:
-		return 0;
 	case PCH_DEVFN_GSPI0:
 		return 1;
 	case PCH_DEVFN_GSPI1:

src/soc/intel/tigerlake/spi.c

@@ -16,8 +16,6 @@
 int spi_soc_devfn_to_bus(unsigned int devfn)
 {
 	switch (devfn) {
-	case PCH_DEVFN_SPI:
-		return 0;
 	case PCH_DEVFN_GSPI0:
 		return 1;
 	case PCH_DEVFN_GSPI1: