src/arch: Capitalize CPU, RAM and ROM
Change-Id: Ia6ac94a93b48037a392a9aec2cd19cd80369173f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15953 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
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@ -28,7 +28,7 @@
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ENTRY(_start)
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/*
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* Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data
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* Set the CPU to System mode with IRQ and FIQ disabled. Prefetch/Data
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* aborts may happen early and crash before the abort handlers are
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* installed, but at least the problem will show up near the code that
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* causes it.
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@ -39,7 +39,7 @@ maskrom_param:
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ENTRY(_start)
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/*
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* Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data
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* Set the CPU to System mode with IRQ and FIQ disabled. Prefetch/Data
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* aborts may happen early and crash before the abort handlers are
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* installed, but at least the problem will show up near the code that
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* causes it.
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@ -30,7 +30,7 @@
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#include <stdlib.h>
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#include <arch/cpu.h>
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/* Return the cpu struct which is at the high memory address of the stack.
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/* Return the CPU struct which is at the high memory address of the stack.
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*/
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struct cpu_info *cpu_info(void)
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{
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@ -190,7 +190,7 @@ config VERSTAGE_ADDR
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default 0x2000000
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# Use the post CAR infrastructure for tearing down cache-as-ram
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# from a program loaded in ram and subsequently loading ramstage.
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# from a program loaded in RAM and subsequently loading ramstage.
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config POSTCAR_STAGE
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def_bool n
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@ -77,7 +77,7 @@ _start:
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/* Push the thread pointer. */
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push $0
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#endif
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/* Push the cpu index and struct cpu */
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/* Push the CPU index and struct CPU */
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push $0
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push $0
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@ -331,12 +331,12 @@ gdtaddr:
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* which is defined in entry32.inc
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*
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* When the machine is initially started, we use a very simple
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* gdt from rom (that in entry32.inc) which only contains those
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* gdt from ROM (that in entry32.inc) which only contains those
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* entries we need for protected mode.
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*
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* When we're executing code from RAM, we want to do more complex
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* stuff, like initializing PCI option roms in real mode, or doing
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* a resume from a suspend to ram.
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* stuff, like initializing PCI option ROMs in real mode, or doing
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* a resume from a suspend to RAM.
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*/
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gdt:
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/* selgdt 0, unused */
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@ -96,7 +96,7 @@ static int deep_magic_nexgen_probe(void)
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}
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#endif
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/* List of cpu vendor strings along with their normalized
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/* List of CPU vendor strings along with their normalized
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* id values.
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*/
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static struct {
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@ -132,7 +132,7 @@ static const char *x86_vendor_name[] = {
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static const char *cpu_vendor_name(int vendor)
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{
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const char *name;
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name = "<invalid cpu vendor>";
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name = "<invalid CPU vendor>";
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if ((vendor < (ARRAY_SIZE(x86_vendor_name))) &&
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(x86_vendor_name[vendor] != 0))
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{
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@ -246,7 +246,7 @@ void cpu_initialize(unsigned int index)
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cpu = info->cpu;
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if (!cpu) {
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die("CPU: missing cpu device structure");
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die("CPU: missing CPU device structure");
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}
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if (cpu->initialized)
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@ -254,7 +254,7 @@ void cpu_initialize(unsigned int index)
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post_log_path(cpu);
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/* Find what type of cpu we are dealing with */
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/* Find what type of CPU we are dealing with */
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identify_cpu(cpu);
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printk(BIOS_DEBUG, "CPU: vendor %s device %x\n",
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cpu_vendor_name(cpu->vendor), cpu->device);
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@ -273,11 +273,11 @@ void cpu_initialize(unsigned int index)
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set_cpu_ops(cpu);
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cpu->device += c.x86_mask;
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if(!cpu->ops) die("Unknown cpu");
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printk(BIOS_DEBUG, "Using generic cpu ops (good)\n");
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printk(BIOS_DEBUG, "Using generic CPU ops (good)\n");
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}
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/* Initialize the cpu */
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/* Initialize the CPU */
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if (cpu->ops && cpu->ops->init) {
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cpu->enabled = 1;
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cpu->initialized = 1;
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@ -420,7 +420,7 @@ void x86_exception(struct eregs *info)
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out_buffer[2] = hexchars[signo & 0xf];
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out_buffer[3] = '\0';
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break;
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case 'g': /* return the value of the cpu registers */
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case 'g': /* return the value of the CPU registers */
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copy_to_hex(out_buffer, &gdb_stub_registers, sizeof(gdb_stub_registers));
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break;
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case 'G': /* set the value of the CPU registers - return OK */
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@ -19,7 +19,7 @@
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#include <rules.h>
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#if ENV_BOOTBLOCK || ENV_ROMSTAGE || ENV_VERSTAGE
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/* No .data or .bss sections. Cache as ram is handled separately. */
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/* No .data or .bss sections. Cache as RAM is handled separately. */
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#define ARCH_STAGE_HAS_DATA_SECTION 0
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#define ARCH_STAGE_HAS_BSS_SECTION 0
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#endif
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@ -18,7 +18,7 @@
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#define __ARCH_SYMBOLS_H
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/*
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* The _car_region_[start|end] covers the entirety of the cache as ram
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* The _car_region_[start|end] covers the entirety of the cache as RAM
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* region. All other symbols with the _car prefix a subsets of this
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* larger region.
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*/
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@ -47,7 +47,7 @@ walkcbfs_asm:
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mov CBFS_HEADER_ROMSIZE(%eax), %ecx
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bswap %ecx
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mov $0, %ebx
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sub %ecx, %ebx /* rom base address in ebx */
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sub %ecx, %ebx /* ROM base address in ebx */
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mov CBFS_HEADER_OFFSET(%eax), %ecx
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bswap %ecx
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add %ecx, %ebx /* address where we start looking for LARCHIVEs */
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