src/arch: Capitalize CPU, RAM and ROM

Change-Id: Ia6ac94a93b48037a392a9aec2cd19cd80369173f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15953
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Elyes HAOUAS 2016-07-29 07:40:41 +02:00 committed by Martin Roth
parent 45de1fe4fb
commit 777ea897e8
10 changed files with 18 additions and 18 deletions

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@ -28,7 +28,7 @@
ENTRY(_start)
/*
* Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data
* Set the CPU to System mode with IRQ and FIQ disabled. Prefetch/Data
* aborts may happen early and crash before the abort handlers are
* installed, but at least the problem will show up near the code that
* causes it.

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@ -39,7 +39,7 @@ maskrom_param:
ENTRY(_start)
/*
* Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data
* Set the CPU to System mode with IRQ and FIQ disabled. Prefetch/Data
* aborts may happen early and crash before the abort handlers are
* installed, but at least the problem will show up near the code that
* causes it.

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@ -30,7 +30,7 @@
#include <stdlib.h>
#include <arch/cpu.h>
/* Return the cpu struct which is at the high memory address of the stack.
/* Return the CPU struct which is at the high memory address of the stack.
*/
struct cpu_info *cpu_info(void)
{

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@ -190,7 +190,7 @@ config VERSTAGE_ADDR
default 0x2000000
# Use the post CAR infrastructure for tearing down cache-as-ram
# from a program loaded in ram and subsequently loading ramstage.
# from a program loaded in RAM and subsequently loading ramstage.
config POSTCAR_STAGE
def_bool n

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@ -77,7 +77,7 @@ _start:
/* Push the thread pointer. */
push $0
#endif
/* Push the cpu index and struct cpu */
/* Push the CPU index and struct CPU */
push $0
push $0
@ -331,12 +331,12 @@ gdtaddr:
* which is defined in entry32.inc
*
* When the machine is initially started, we use a very simple
* gdt from rom (that in entry32.inc) which only contains those
* gdt from ROM (that in entry32.inc) which only contains those
* entries we need for protected mode.
*
* When we're executing code from RAM, we want to do more complex
* stuff, like initializing PCI option roms in real mode, or doing
* a resume from a suspend to ram.
* stuff, like initializing PCI option ROMs in real mode, or doing
* a resume from a suspend to RAM.
*/
gdt:
/* selgdt 0, unused */

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@ -96,7 +96,7 @@ static int deep_magic_nexgen_probe(void)
}
#endif
/* List of cpu vendor strings along with their normalized
/* List of CPU vendor strings along with their normalized
* id values.
*/
static struct {
@ -132,7 +132,7 @@ static const char *x86_vendor_name[] = {
static const char *cpu_vendor_name(int vendor)
{
const char *name;
name = "<invalid cpu vendor>";
name = "<invalid CPU vendor>";
if ((vendor < (ARRAY_SIZE(x86_vendor_name))) &&
(x86_vendor_name[vendor] != 0))
{
@ -246,7 +246,7 @@ void cpu_initialize(unsigned int index)
cpu = info->cpu;
if (!cpu) {
die("CPU: missing cpu device structure");
die("CPU: missing CPU device structure");
}
if (cpu->initialized)
@ -254,7 +254,7 @@ void cpu_initialize(unsigned int index)
post_log_path(cpu);
/* Find what type of cpu we are dealing with */
/* Find what type of CPU we are dealing with */
identify_cpu(cpu);
printk(BIOS_DEBUG, "CPU: vendor %s device %x\n",
cpu_vendor_name(cpu->vendor), cpu->device);
@ -273,11 +273,11 @@ void cpu_initialize(unsigned int index)
set_cpu_ops(cpu);
cpu->device += c.x86_mask;
if(!cpu->ops) die("Unknown cpu");
printk(BIOS_DEBUG, "Using generic cpu ops (good)\n");
printk(BIOS_DEBUG, "Using generic CPU ops (good)\n");
}
/* Initialize the cpu */
/* Initialize the CPU */
if (cpu->ops && cpu->ops->init) {
cpu->enabled = 1;
cpu->initialized = 1;

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@ -420,7 +420,7 @@ void x86_exception(struct eregs *info)
out_buffer[2] = hexchars[signo & 0xf];
out_buffer[3] = '\0';
break;
case 'g': /* return the value of the cpu registers */
case 'g': /* return the value of the CPU registers */
copy_to_hex(out_buffer, &gdb_stub_registers, sizeof(gdb_stub_registers));
break;
case 'G': /* set the value of the CPU registers - return OK */

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@ -19,7 +19,7 @@
#include <rules.h>
#if ENV_BOOTBLOCK || ENV_ROMSTAGE || ENV_VERSTAGE
/* No .data or .bss sections. Cache as ram is handled separately. */
/* No .data or .bss sections. Cache as RAM is handled separately. */
#define ARCH_STAGE_HAS_DATA_SECTION 0
#define ARCH_STAGE_HAS_BSS_SECTION 0
#endif

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@ -18,7 +18,7 @@
#define __ARCH_SYMBOLS_H
/*
* The _car_region_[start|end] covers the entirety of the cache as ram
* The _car_region_[start|end] covers the entirety of the cache as RAM
* region. All other symbols with the _car prefix a subsets of this
* larger region.
*/

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@ -47,7 +47,7 @@ walkcbfs_asm:
mov CBFS_HEADER_ROMSIZE(%eax), %ecx
bswap %ecx
mov $0, %ebx
sub %ecx, %ebx /* rom base address in ebx */
sub %ecx, %ebx /* ROM base address in ebx */
mov CBFS_HEADER_OFFSET(%eax), %ecx
bswap %ecx
add %ecx, %ebx /* address where we start looking for LARCHIVEs */