sc7180: Provide initial SoC support
Change-Id: Iddcef560c1987486436b73ca1d5fc83cee2f713c Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
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@ -7,3 +7,4 @@ This section contains documentation about coreboot on specific SOCs.
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- [AMD](amd/index.md)
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- [Cavium](cavium/index.md)
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- [Intel](intel/index.md)
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- [Qualcomm](qualcomm/index.md)
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@ -0,0 +1,7 @@
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# Qualcomm SOC-specific documentation
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This section contains documentation about coreboot on specific Qualcomm SOCs.
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## Platforms
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- [SC7180 series](sc7180/index.md)
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@ -0,0 +1,19 @@
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# Qualcomm SC7180 documentation
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## SOC code
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The SOC folder contains functions for:
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* MMU
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* CLOCK
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* GPIO
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* QUPv3 FW (provides a bridge to serial interfaces)
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* UART
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* SPI-NOR
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* AOP FW
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* USB
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## Notes about the hardware
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The timer is used from the ARMv8 architecture specific code.
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@ -0,0 +1,23 @@
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config SOC_QUALCOMM_SC7180
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bool
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default n
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select ARCH_BOOTBLOCK_ARMV8_64
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select ARCH_RAMSTAGE_ARMV8_64
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select ARCH_ROMSTAGE_ARMV8_64
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select ARCH_VERSTAGE_ARMV8_64
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select GENERIC_GPIO_LIB
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select GENERIC_UDELAY
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select HAVE_MONOTONIC_TIMER
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select ARM64_USE_ARCH_TIMER
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select SOC_QUALCOMM_COMMON
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if SOC_QUALCOMM_SC7180
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config VBOOT
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select VBOOT_SEPARATE_VERSTAGE
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select VBOOT_RETURN_FROM_VERSTAGE
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select VBOOT_MUST_REQUEST_DISPLAY
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select VBOOT_STARTS_IN_BOOTBLOCK
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endif
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@ -0,0 +1,36 @@
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ifeq ($(CONFIG_SOC_QUALCOMM_SC7180),y)
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################################################################################
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bootblock-y += bootblock.c
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bootblock-y += mmu.c
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bootblock-y += timer.c
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bootblock-y += spi.c
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################################################################################
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verstage-y += timer.c
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verstage-y += spi.c
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################################################################################
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romstage-y += cbmem.c
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romstage-y += timer.c
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romstage-y += ../common/qclib.c
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romstage-y += qclib.c
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romstage-y += ../common/mmu.c
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romstage-y += mmu.c
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romstage-y += spi.c
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################################################################################
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ramstage-y += soc.c
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ramstage-y += cbmem.c
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ramstage-y += timer.c
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ramstage-y += spi.c
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################################################################################
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CPPFLAGS_common += -Isrc/soc/qualcomm/sc7180/include
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CPPFLAGS_common += -Isrc/soc/qualcomm/common/include
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################################################################################
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endif
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@ -0,0 +1,22 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018-2019, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <bootblock_common.h>
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#include <soc/mmu.h>
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void bootblock_soc_init(void)
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{
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sc7180_mmu_init();
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}
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@ -0,0 +1,21 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018-2019, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <cbmem.h>
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void *cbmem_top(void)
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{
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return (void *)((uintptr_t)4 * GiB);
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}
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@ -0,0 +1,21 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (c) 2018-2019 Qualcomm Technologies
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _SOC_QUALCOMM_SC7180_ADDRESS_MAP_H_
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#define _SOC_QUALCOMM_SC7180_ADDRESS_MAP_H_
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#include <stdint.h>
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#endif /* _SOC_QUALCOMM_SC7180_ADDRESS_MAP_H_ */
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@ -0,0 +1,26 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018-2019, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _SOC_QUALCOMM_SC7180_GPIO_H_
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#define _SOC_QUALCOMM_SC7180_GPIO_H_
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#include <types.h>
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typedef struct {
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u32 addr;
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} gpio_t;
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#endif /* _SOC_QUALCOMM_SC7180_GPIO_H_ */
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@ -0,0 +1,58 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018-2019, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <memlayout.h>
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#include <arch/header.ld>
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/* SYSTEM_IMEM : 0x14680000 - 0x146AE000 */
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#define SSRAM_START(addr) SYMBOL(ssram, addr)
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#define SSRAM_END(addr) SYMBOL(essram, addr)
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/* BOOT_IMEM : 0x14800000 - 0x14980000 */
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#define BSRAM_START(addr) SYMBOL(bsram, addr)
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#define BSRAM_END(addr) SYMBOL(ebsram, addr)
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SECTIONS
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{
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SSRAM_START(0x14680000)
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OVERLAP_VERSTAGE_ROMSTAGE(0x14680000, 100K)
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REGION(qcsdi, 0x14699000, 52K, 4K)
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SSRAM_END(0x146AE000)
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BSRAM_START(0x14800000)
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BOOTBLOCK(0x14815000, 40K)
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PRERAM_CBFS_CACHE(0x1481F000, 70K)
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PRERAM_CBMEM_CONSOLE(0x14830800, 32K)
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TIMESTAMP(0x14838800, 1K)
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TTB(0x14839000, 56K)
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STACK(0x14847000, 16K)
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VBOOT2_WORK(0x1484B000, 12K)
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DMA_COHERENT(0x1484E000, 8K)
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REGION(ddr_training, 0x14850000, 8K, 4K)
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REGION(qclib_serial_log, 0x14852000, 4K, 4K)
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REGION(ddr_information, 0x14853000, 1K, 1K)
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REGION(dcb, 0x14870000, 16K, 4K)
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REGION(pmic, 0x14874000, 44K, 4K)
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REGION(limits_cfg, 0x1487F000, 4K, 4K)
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REGION(qclib, 0x14880000, 512K, 4K)
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BSRAM_END(0x14900000)
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DRAM_START(0x80000000)
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/* Various hardware/software subsystems make use of this area */
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REGION(dram_soc, 0x80900000, 0x300000, 0x1000)
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BL31(0x80C00000, 0x1A800000)
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POSTRAM_CBFS_CACHE(0x9F800000, 16M)
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RAMSTAGE(0xA0800000, 16M)
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}
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@ -0,0 +1,21 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018-2019, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _SOC_QUALCOMM_SC7180_MMU_H_
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#define _SOC_QUALCOMM_SC7180_MMU_H_
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void sc7180_mmu_init(void);
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#endif /* _SOC_QUALCOMM_SC7180_MMU_H_ */
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@ -0,0 +1,29 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018-2019, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _SOC_QUALCOMM_SC7180_SYMBOLS_H_
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#define _SOC_QUALCOMM_SC7180_SYMBOLS_H_
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#include <symbols.h>
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DECLARE_REGION(ssram)
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DECLARE_REGION(bsram)
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DECLARE_REGION(dram_aop)
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DECLARE_REGION(dram_soc)
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DECLARE_REGION(dcb)
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DECLARE_REGION(pmic)
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DECLARE_REGION(limits_cfg)
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#endif /* _SOC_QUALCOMM_SC7180_SYMBOLS_H_ */
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@ -0,0 +1,34 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018-2019, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <symbols.h>
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#include <arch/mmu.h>
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#include <arch/cache.h>
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#include <soc/mmu.h>
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#include <soc/mmu_common.h>
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#include <soc/symbols.h>
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void sc7180_mmu_init(void)
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{
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mmu_init();
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mmu_config_range((void *)(4 * KiB), ((4UL * GiB) - (4 * KiB)), DEV_MEM);
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mmu_config_range((void *)_ssram, REGION_SIZE(ssram), CACHED_RAM);
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mmu_config_range((void *)_bsram, REGION_SIZE(bsram), CACHED_RAM);
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mmu_config_range((void *)_dma_coherent, REGION_SIZE(dma_coherent),
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UNCACHED_RAM);
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mmu_enable();
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}
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@ -0,0 +1,50 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <cbfs.h>
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#include <fmap.h>
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#include <console/console.h>
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#include <soc/symbols.h>
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#include <soc/qclib_common.h>
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int qclib_soc_blob_load(void)
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{
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size_t size;
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ssize_t ssize;
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/* Attempt to load PMICCFG Blob */
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size = cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/pmiccfg",
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_pmic, REGION_SIZE(pmic), CBFS_TYPE_RAW);
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if (!size)
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return -1;
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qclib_add_if_table_entry(QCLIB_TE_PMIC_SETTINGS, _pmic, size, 0);
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/* Attempt to load DCB Blob */
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size = cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/dcb",
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_dcb, REGION_SIZE(dcb), CBFS_TYPE_RAW);
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if (!size)
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return -1;
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qclib_add_if_table_entry(QCLIB_TE_DCB_SETTINGS, _dcb, size, 0);
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/* Attempt to load Limits Config Blob */
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ssize = fmap_read_area(QCLIB_FR_LIMITS_CFG_DATA, _limits_cfg,
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REGION_SIZE(limits_cfg));
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if (ssize < 0)
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return -1;
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qclib_add_if_table_entry(QCLIB_TE_LIMITS_CFG_DATA,
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_limits_cfg, ssize, 0);
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return 0;
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}
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@ -0,0 +1,48 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018-2019, The Linux Foundation. All rights reserved.
|
||||
*
|
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
|
||||
*
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* This program is distributed in the hope that it will be useful,
|
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
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*/
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#include <symbols.h>
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#include <device/device.h>
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#include <soc/mmu.h>
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#include <soc/mmu_common.h>
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#include <soc/symbols.h>
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static void soc_read_resources(struct device *dev)
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{
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ram_resource(dev, 0, (uintptr_t)ddr_region->offset / KiB,
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ddr_region->size / KiB);
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reserved_ram_resource(dev, 1, (uintptr_t)_dram_soc / KiB,
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REGION_SIZE(dram_soc) / KiB);
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}
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static void soc_init(struct device *dev)
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{
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}
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static struct device_operations soc_ops = {
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.read_resources = soc_read_resources,
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.init = soc_init,
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};
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static void enable_soc_dev(struct device *dev)
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{
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dev->ops = &soc_ops;
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}
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struct chip_operations soc_qualcomm_sc7180_ops = {
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CHIP_NAME("SOC Qualcomm SC7180")
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.enable_dev = enable_soc_dev,
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};
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@ -0,0 +1,29 @@
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/*
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* This file is part of the coreboot project.
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*
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||||
* Copyright (C) 2018, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
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#include <spi-generic.h>
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#include <spi_flash.h>
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static const struct spi_ctrlr spi_ctrlr;
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const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
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{
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.ctrlr = &spi_ctrlr,
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.bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS,
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.bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS,
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},
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};
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const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);
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/*
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* This file is part of the coreboot project.
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*
|
||||
* Copyright (C) 2018-2019, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <delay.h>
|
||||
#include <arch/lib_helpers.h>
|
||||
#include <commonlib/helpers.h>
|
||||
|
||||
void init_timer(void)
|
||||
{
|
||||
raw_write_cntfrq_el0(19200*KHz);
|
||||
}
|
Loading…
Reference in New Issue