sc7180: Provide initial SoC support

Change-Id: Iddcef560c1987486436b73ca1d5fc83cee2f713c
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>

Documentation/soc/index.md

@@ -7,3 +7,4 @@ This section contains documentation about coreboot on specific SOCs.
 - [AMD](amd/index.md)
 - [Cavium](cavium/index.md)
 - [Intel](intel/index.md)
+- [Qualcomm](qualcomm/index.md)

Documentation/soc/qualcomm/index.md

@@ -0,0 +1,7 @@
+# Qualcomm SOC-specific documentation
+
+This section contains documentation about coreboot on specific Qualcomm SOCs.
+
+## Platforms
+
+- [SC7180 series](sc7180/index.md)

Documentation/soc/qualcomm/sc7180/index.md

@@ -0,0 +1,19 @@
+# Qualcomm SC7180 documentation
+
+## SOC code
+
+The SOC folder contains functions for:
+* MMU
+* CLOCK
+* GPIO
+* QUPv3 FW (provides a bridge to serial interfaces)
+* UART
+* SPI-NOR
+* AOP FW
+* USB
+
+## Notes about the hardware
+
+The timer is used from the ARMv8 architecture specific code.
+
+

src/soc/qualcomm/sc7180/Kconfig

@@ -0,0 +1,23 @@
+
+config SOC_QUALCOMM_SC7180
+	bool
+	default n
+	select ARCH_BOOTBLOCK_ARMV8_64
+	select ARCH_RAMSTAGE_ARMV8_64
+	select ARCH_ROMSTAGE_ARMV8_64
+	select ARCH_VERSTAGE_ARMV8_64
+	select GENERIC_GPIO_LIB
+	select GENERIC_UDELAY
+	select HAVE_MONOTONIC_TIMER
+	select ARM64_USE_ARCH_TIMER
+	select SOC_QUALCOMM_COMMON
+
+if SOC_QUALCOMM_SC7180
+
+config VBOOT
+	select VBOOT_SEPARATE_VERSTAGE
+	select VBOOT_RETURN_FROM_VERSTAGE
+	select VBOOT_MUST_REQUEST_DISPLAY
+	select VBOOT_STARTS_IN_BOOTBLOCK
+
+endif

src/soc/qualcomm/sc7180/Makefile.inc

@@ -0,0 +1,36 @@
+
+ifeq ($(CONFIG_SOC_QUALCOMM_SC7180),y)
+
+################################################################################
+bootblock-y += bootblock.c
+bootblock-y += mmu.c
+bootblock-y += timer.c
+bootblock-y += spi.c
+
+################################################################################
+verstage-y += timer.c
+verstage-y += spi.c
+
+################################################################################
+romstage-y += cbmem.c
+romstage-y += timer.c
+romstage-y += ../common/qclib.c
+romstage-y += qclib.c
+romstage-y += ../common/mmu.c
+romstage-y += mmu.c
+romstage-y += spi.c
+
+################################################################################
+ramstage-y += soc.c
+ramstage-y += cbmem.c
+ramstage-y += timer.c
+ramstage-y += spi.c
+
+################################################################################
+
+CPPFLAGS_common += -Isrc/soc/qualcomm/sc7180/include
+CPPFLAGS_common += -Isrc/soc/qualcomm/common/include
+
+################################################################################
+
+endif

src/soc/qualcomm/sc7180/bootblock.c

@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018-2019, The Linux Foundation.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootblock_common.h>
+#include <soc/mmu.h>
+
+void bootblock_soc_init(void)
+{
+	sc7180_mmu_init();
+}

src/soc/qualcomm/sc7180/cbmem.c

@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018-2019, The Linux Foundation.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <cbmem.h>
+
+void *cbmem_top(void)
+{
+	return (void *)((uintptr_t)4 * GiB);
+}

src/soc/qualcomm/sc7180/include/soc/addressmap.h

@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2018-2019 Qualcomm Technologies
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_QUALCOMM_SC7180_ADDRESS_MAP_H_
+#define _SOC_QUALCOMM_SC7180_ADDRESS_MAP_H_
+
+#include <stdint.h>
+
+#endif /* _SOC_QUALCOMM_SC7180_ADDRESS_MAP_H_ */

src/soc/qualcomm/sc7180/include/soc/gpio.h

@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018-2019, The Linux Foundation.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_QUALCOMM_SC7180_GPIO_H_
+#define _SOC_QUALCOMM_SC7180_GPIO_H_
+
+#include <types.h>
+
+typedef struct {
+	u32 addr;
+} gpio_t;
+
+
+#endif /* _SOC_QUALCOMM_SC7180_GPIO_H_ */

src/soc/qualcomm/sc7180/include/soc/memlayout.ld

@@ -0,0 +1,58 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018-2019, The Linux Foundation.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <memlayout.h>
+#include <arch/header.ld>
+
+/* SYSTEM_IMEM : 0x14680000 - 0x146AE000 */
+#define SSRAM_START(addr) SYMBOL(ssram, addr)
+#define SSRAM_END(addr) SYMBOL(essram, addr)
+
+/* BOOT_IMEM   : 0x14800000 - 0x14980000 */
+#define BSRAM_START(addr) SYMBOL(bsram, addr)
+#define BSRAM_END(addr) SYMBOL(ebsram, addr)
+
+SECTIONS
+{
+	SSRAM_START(0x14680000)
+	OVERLAP_VERSTAGE_ROMSTAGE(0x14680000, 100K)
+	REGION(qcsdi, 0x14699000, 52K, 4K)
+	SSRAM_END(0x146AE000)
+
+	BSRAM_START(0x14800000)
+	BOOTBLOCK(0x14815000, 40K)
+	PRERAM_CBFS_CACHE(0x1481F000, 70K)
+	PRERAM_CBMEM_CONSOLE(0x14830800, 32K)
+	TIMESTAMP(0x14838800, 1K)
+	TTB(0x14839000, 56K)
+	STACK(0x14847000, 16K)
+	VBOOT2_WORK(0x1484B000, 12K)
+	DMA_COHERENT(0x1484E000, 8K)
+	REGION(ddr_training, 0x14850000, 8K, 4K)
+	REGION(qclib_serial_log, 0x14852000, 4K, 4K)
+	REGION(ddr_information, 0x14853000, 1K, 1K)
+	REGION(dcb, 0x14870000, 16K, 4K)
+	REGION(pmic, 0x14874000, 44K, 4K)
+	REGION(limits_cfg, 0x1487F000, 4K, 4K)
+	REGION(qclib, 0x14880000, 512K, 4K)
+	BSRAM_END(0x14900000)
+
+	DRAM_START(0x80000000)
+	/* Various hardware/software subsystems make use of this area */
+	REGION(dram_soc,  0x80900000, 0x300000, 0x1000)
+	BL31(0x80C00000, 0x1A800000)
+	POSTRAM_CBFS_CACHE(0x9F800000, 16M)
+	RAMSTAGE(0xA0800000, 16M)
+}

src/soc/qualcomm/sc7180/include/soc/mmu.h

@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018-2019, The Linux Foundation.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_QUALCOMM_SC7180_MMU_H_
+#define _SOC_QUALCOMM_SC7180_MMU_H_
+
+void sc7180_mmu_init(void);
+
+#endif /* _SOC_QUALCOMM_SC7180_MMU_H_ */

src/soc/qualcomm/sc7180/include/soc/symbols.h

@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018-2019, The Linux Foundation.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_QUALCOMM_SC7180_SYMBOLS_H_
+#define _SOC_QUALCOMM_SC7180_SYMBOLS_H_
+
+#include <symbols.h>
+
+DECLARE_REGION(ssram)
+DECLARE_REGION(bsram)
+DECLARE_REGION(dram_aop)
+DECLARE_REGION(dram_soc)
+DECLARE_REGION(dcb)
+DECLARE_REGION(pmic)
+DECLARE_REGION(limits_cfg)
+
+#endif /* _SOC_QUALCOMM_SC7180_SYMBOLS_H_ */

src/soc/qualcomm/sc7180/mmu.c

@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018-2019, The Linux Foundation.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <symbols.h>
+#include <arch/mmu.h>
+#include <arch/cache.h>
+#include <soc/mmu.h>
+#include <soc/mmu_common.h>
+#include <soc/symbols.h>
+
+void sc7180_mmu_init(void)
+{
+	mmu_init();
+
+	mmu_config_range((void *)(4 * KiB), ((4UL * GiB) - (4 * KiB)), DEV_MEM);
+	mmu_config_range((void *)_ssram, REGION_SIZE(ssram), CACHED_RAM);
+	mmu_config_range((void *)_bsram, REGION_SIZE(bsram), CACHED_RAM);
+	mmu_config_range((void *)_dma_coherent, REGION_SIZE(dma_coherent),
+			 UNCACHED_RAM);
+
+	mmu_enable();
+}

src/soc/qualcomm/sc7180/qclib.c

@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <cbfs.h>
+#include <fmap.h>
+#include <console/console.h>
+#include <soc/symbols.h>
+#include <soc/qclib_common.h>
+
+int qclib_soc_blob_load(void)
+{
+	size_t size;
+	ssize_t ssize;
+
+	/* Attempt to load PMICCFG Blob */
+	size = cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/pmiccfg",
+			_pmic, REGION_SIZE(pmic), CBFS_TYPE_RAW);
+	if (!size)
+		return -1;
+	qclib_add_if_table_entry(QCLIB_TE_PMIC_SETTINGS, _pmic, size, 0);
+
+	/* Attempt to load DCB Blob */
+	size = cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/dcb",
+			_dcb, REGION_SIZE(dcb), CBFS_TYPE_RAW);
+	if (!size)
+		return -1;
+	qclib_add_if_table_entry(QCLIB_TE_DCB_SETTINGS, _dcb, size, 0);
+
+	/* Attempt to load Limits Config Blob */
+	ssize = fmap_read_area(QCLIB_FR_LIMITS_CFG_DATA, _limits_cfg,
+		REGION_SIZE(limits_cfg));
+	if (ssize < 0)
+		return -1;
+	qclib_add_if_table_entry(QCLIB_TE_LIMITS_CFG_DATA,
+				 _limits_cfg, ssize, 0);
+
+	return 0;
+}

src/soc/qualcomm/sc7180/soc.c

@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018-2019, The Linux Foundation.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <symbols.h>
+#include <device/device.h>
+#include <soc/mmu.h>
+#include <soc/mmu_common.h>
+#include <soc/symbols.h>
+
+static void soc_read_resources(struct device *dev)
+{
+	ram_resource(dev, 0, (uintptr_t)ddr_region->offset / KiB,
+				ddr_region->size / KiB);
+	reserved_ram_resource(dev, 1, (uintptr_t)_dram_soc / KiB,
+				REGION_SIZE(dram_soc) / KiB);
+}
+
+static void soc_init(struct device *dev)
+{
+
+}
+
+static struct device_operations soc_ops = {
+	.read_resources = soc_read_resources,
+	.init = soc_init,
+};
+
+static void enable_soc_dev(struct device *dev)
+{
+	dev->ops = &soc_ops;
+}
+
+struct chip_operations soc_qualcomm_sc7180_ops = {
+	CHIP_NAME("SOC Qualcomm SC7180")
+	.enable_dev = enable_soc_dev,
+};

src/soc/qualcomm/sc7180/spi.c

@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <spi-generic.h>
+#include <spi_flash.h>
+
+static const struct spi_ctrlr spi_ctrlr;
+
+const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
+	{
+		.ctrlr = &spi_ctrlr,
+		.bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS,
+		.bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS,
+	},
+};
+
+const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);

src/soc/qualcomm/sc7180/timer.c

@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018-2019, The Linux Foundation.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <delay.h>
+#include <arch/lib_helpers.h>
+#include <commonlib/helpers.h>
+
+void init_timer(void)
+{
+	raw_write_cntfrq_el0(19200*KHz);
+}