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intel/lynxpoint: Export pch_enable_lpc() for Super I/O systems 

In order to enable a Super I/O in non Chrome EC systems we
need to make pch_enable_lpc() available to the mainboard
romstage.c

BUG=none
BRANCH=none
TEST=boot ChromeOS on Beltino

Change-Id: I34e7d23012e1852c69e82ba7cdc81a05751846de
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172180
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/6019
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
Stefan Reinauer 2013-10-07 16:29:54 -07:00 committed by Patrick Georgi
parent c50c0ab456
commit 779e178353
2 changed files with 2 additions and 1 deletions
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2
src/southbridge/intel/lynxpoint/early_pch.c
View File

@ -102,7 +102,7 @@ static int sleep_type_s3(void)
return is_s3; return is_s3;
} }
static void pch_enable_lpc(void) void pch_enable_lpc(void)
{ {
const struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); const struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
const struct southbridge_intel_lynxpoint_config *config = NULL; const struct southbridge_intel_lynxpoint_config *config = NULL;

1
src/southbridge/intel/lynxpoint/pch.h
View File

@ -213,6 +213,7 @@ int smbus_read_byte(unsigned device, unsigned address);
int early_spi_read(u32 offset, u32 size, u8 *buffer); int early_spi_read(u32 offset, u32 size, u8 *buffer);
int early_pch_init(const void *gpio_map, int early_pch_init(const void *gpio_map,
const struct rcba_config_instruction *rcba_config); const struct rcba_config_instruction *rcba_config);
void pch_enable_lpc(void);
#endif /* !__PRE_RAM__ && !__SMM__ */ #endif /* !__PRE_RAM__ && !__SMM__ */
#endif /* __ASSEMBLER__ */ #endif /* __ASSEMBLER__ */