GNUBoot/coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

nb/amd: add IS_ENABLED() around Kconfig symbol references

Browse source 
Some of these can be changed from #if to if(), but that will happen
in a follow-on commmit.

Change-Id: I763cbbc31dcd4cdd128c04793a742ab6daaf5f0c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Martin Roth 2017-06-24 14:45:48 -06:00
parent 3c35ad9053
commit 77a58b92e8
29 changed files with 148 additions and 147 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

10
src/northbridge/amd/agesa/family10/northbridge.c
View file

@ -27,7 +27,7 @@
#include <cpu/x86/lapic.h>
#include <cbmem.h>
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
#include <pc80/mc146818rtc.h>
#endif
@ -496,7 +496,7 @@ static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid)
* we only deal with the 'first' vga card */
for (link = dev->link_list; link; link = link->next) {
if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
#if CONFIG_MULTIPLE_VGA_ADAPTERS
#if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)
extern device_t vga_pri; // the primary vga device, defined in device.c
printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
link->secondary,link->subordinate);
@ -800,7 +800,7 @@ static void amdfam10_domain_set_resources(device_t dev)
ramtop = limitk * 1024;
}
#if CONFIG_GFXUMA
#if IS_ENABLED(CONFIG_GFXUMA)
set_top_of_ram(uma_memory_base);
uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10);
#else
@ -942,7 +942,7 @@ static void cpu_bus_scan(device_t dev)
}
disable_siblings = !CONFIG_LOGICAL_CPUS;
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
get_option(&disable_siblings, "multi_core");
#endif
@ -1117,7 +1117,7 @@ static void root_complex_enable_dev(struct device *dev)
the global uma_memory variables already in its enable function. */
if (!done) {
setup_bsp_ramtop();
#if CONFIG_GFXUMA
#if IS_ENABLED(CONFIG_GFXUMA)
#error Northbridge does not set uma_memory_base or uma_memory_size.
setup_uma_memory();
#endif

6
src/northbridge/amd/agesa/family12/northbridge.c
View file

@ -362,7 +362,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid)
}
#if CONFIG_CONSOLE_VGA_MULTI
#if IS_ENABLED(CONFIG_CONSOLE_VGA_MULTI)
extern device_t vga_pri; // the primary vga device, defined in device.c
#endif
@ -376,7 +376,7 @@ printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__);
* we only deal with the 'first' vga card */
for (link = dev->link_list; link; link = link->next) {
if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
#if CONFIG_CONSOLE_VGA_MULTI
#if IS_ENABLED(CONFIG_CONSOLE_VGA_MULTI)
printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
link->secondary,link->subordinate);
/* We need to make sure the vga_pri is under the link */
@ -600,7 +600,7 @@ static void domain_enable_resources(device_t dev)
printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__);
/* Must be called after PCI enumeration and resource allocation */
#if CONFIG_AMD_SB_CIMX
#if IS_ENABLED(CONFIG_AMD_SB_CIMX)
sb_After_Pci_Init();
sb_Mid_Post_Init();
#endif

6
src/northbridge/amd/agesa/family14/northbridge.c
View file

@ -353,7 +353,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid)
report_resource_stored(dev, resource, buf);
}
#if CONFIG_CONSOLE_VGA_MULTI
#if IS_ENABLED(CONFIG_CONSOLE_VGA_MULTI)
extern device_t vga_pri; // the primary vga device, defined in device.c
#endif
@ -367,7 +367,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid)
* we only deal with the 'first' vga card */
for (link = dev->link_list; link; link = link->next) {
if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
#if CONFIG_CONSOLE_VGA_MULTI
#if IS_ENABLED(CONFIG_CONSOLE_VGA_MULTI)
printk(BIOS_DEBUG,
"VGA: vga_pri bus num = %d bus range [%d,%d]\n",
vga_pri->bus->secondary, link->secondary,
@ -581,7 +581,7 @@ static void domain_set_resources(device_t dev)
static void domain_enable_resources(device_t dev)
{
#if CONFIG_AMD_SB_CIMX
#if IS_ENABLED(CONFIG_AMD_SB_CIMX)
if (!acpi_is_wakeup_s3()) {
sb_After_Pci_Init();
sb_Mid_Post_Init();

6
src/northbridge/amd/agesa/family15/northbridge.c
View file

@ -391,7 +391,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid)
* we only deal with the 'first' vga card */
for (link = dev->link_list; link; link = link->next) {
if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
#if CONFIG_MULTIPLE_VGA_ADAPTERS
#if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)
extern device_t vga_pri; // the primary vga device, defined in device.c
printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
link->secondary,link->subordinate);
@ -640,7 +640,7 @@ static void domain_enable_resources(device_t dev)
/* Must be called after PCI enumeration and resource allocation */
printk(BIOS_DEBUG, "\nFam15 - %s: AmdInitMid.\n", __func__);
#if CONFIG_AMD_SB_CIMX
#if IS_ENABLED(CONFIG_AMD_SB_CIMX)
sb_After_Pci_Init();
#endif
/* Enable MMIO on AMD CPU Address Map Controller */
@ -1021,7 +1021,7 @@ static void cpu_bus_scan(device_t dev)
lapicid_start = (lapicid_start + 1) * core_max;
printk(BIOS_SPEW, "lpaicid_start = 0x%x ", lapicid_start);
}
#if CONFIG_CPU_AMD_SOCKET_G34
#if IS_ENABLED(CONFIG_CPU_AMD_SOCKET_G34)
u32 apic_id = (i / 2 * core_max) + j + lapicid_start + (i % 2 ? siblings + 1 : 0);
#else
u32 apic_id = (i * core_max) + j + lapicid_start;

2
src/northbridge/amd/agesa/family15rl/northbridge.c
View file

@ -390,7 +390,7 @@ static void create_vga_resource(struct device *dev, unsigned nodeid)
* we only deal with the 'first' vga card */
for (link = dev->link_list; link; link = link->next) {
if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
#if CONFIG_MULTIPLE_VGA_ADAPTERS
#if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)
extern struct device *vga_pri; // the primary vga device, defined in device.c
printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
link->secondary,link->subordinate);

2
src/northbridge/amd/agesa/family15tn/northbridge.c
View file

@ -389,7 +389,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid)
* we only deal with the 'first' vga card */
for (link = dev->link_list; link; link = link->next) {
if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
#if CONFIG_MULTIPLE_VGA_ADAPTERS
#if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)
extern device_t vga_pri; // the primary vga device, defined in device.c
printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
link->secondary,link->subordinate);

2
src/northbridge/amd/agesa/family16kb/northbridge.c
View file

@ -389,7 +389,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid)
* we only deal with the 'first' vga card */
for (link = dev->link_list; link; link = link->next) {
if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
#if CONFIG_MULTIPLE_VGA_ADAPTERS
#if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)
extern device_t vga_pri; // the primary vga device, defined in device.c
printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
link->secondary,link->subordinate);

10
src/northbridge/amd/amdfam10/debug.c
View file

@ -21,7 +21,7 @@
void print_debug_addr(const char *str, void *val)
{
#if CONFIG_DEBUG_CAR
#if IS_ENABLED(CONFIG_DEBUG_CAR)
printk(BIOS_DEBUG, "------Address debug: %s%p------\n", str, val);
#endif
}
@ -205,7 +205,7 @@ void dump_pci_devices_on_bus(u32 busn)
}
}
#if CONFIG_DEBUG_SMBUS
#if IS_ENABLED(CONFIG_DEBUG_SMBUS)
void dump_spd_registers(const struct mem_controller *ctrl)
{
int i;
@ -315,14 +315,14 @@ void dump_mem(u32 start, u32 end)
#if IS_ENABLED(CONFIG_DIMM_DDR2)
void print_tx(const char *strval, u32 val)
{
#if CONFIG_DEBUG_RAM_SETUP
#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
printk(BIOS_DEBUG, "%s%08x\n", strval, val);
#endif
}
void print_t(const char *strval)
{
#if CONFIG_DEBUG_RAM_SETUP
#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
printk(BIOS_DEBUG, "%s", strval);
#endif
}
@ -330,7 +330,7 @@ void print_t(const char *strval)
void print_tf(const char *func, const char *strval)
{
#if CONFIG_DEBUG_RAM_SETUP
#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
printk(BIOS_DEBUG, "%s: %s", func, strval);
#endif
}

2
src/northbridge/amd/amdfam10/debug.h
View file

@ -32,7 +32,7 @@ void dump_pci_device_index(u32 dev, u32 index_reg, u32 type, u32 length);
void dump_pci_devices(void);
void dump_pci_devices_on_bus(u32 busn);
#if CONFIG_DEBUG_SMBUS
#if IS_ENABLED(CONFIG_DEBUG_SMBUS)
void dump_spd_registers(const struct mem_controller *ctrl);
void dump_smbus_registers(void);
#endif

2
src/northbridge/amd/amdfam10/early_ht.c
View file

@ -22,7 +22,7 @@
// mmconf is not ready yet
void set_bsp_node_CHtExtNodeCfgEn(void)
{
#if CONFIG_EXT_RT_TBL_SUPPORT
#if IS_ENABLED(CONFIG_EXT_RT_TBL_SUPPORT)
u32 dword;
dword = pci_io_read_config32(PCI_DEV(0, 0x18, 0), 0x68);
dword |= (1<<27) | (1<<25);

22
src/northbridge/amd/amdfam10/northbridge.c
View file

@ -36,7 +36,7 @@
#include <cpu/amd/msr.h>
#include <cpu/amd/family_10h-family_15h/ram_calc.h>
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
#include <cpu/amd/multicore.h>
#include <pc80/mc146818rtc.h>
#endif
@ -50,7 +50,7 @@
#include <cpu/amd/model_10xxx_rev.h>
#endif
#if CONFIG_AMD_SB_CIMX
#if IS_ENABLED(CONFIG_AMD_SB_CIMX)
#include <sb_cimx.h>
#endif
@ -320,7 +320,7 @@ static void amdfam10_scan_chains(device_t dev)
{
struct bus *link;
#if CONFIG_CPU_AMD_SOCKET_G34_NON_AGESA
#if IS_ENABLED(CONFIG_CPU_AMD_SOCKET_G34_NON_AGESA)
if (is_fam15h()) {
uint8_t current_link_number = 0;
@ -585,7 +585,7 @@ static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid)
* we only deal with the 'first' vga card */
for (link = dev->link_list; link; link = link->next) {
if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
#if CONFIG_MULTIPLE_VGA_ADAPTERS
#if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)
extern device_t vga_pri; // the primary vga device, defined in device.c
printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
link->secondary,link->subordinate);
@ -890,7 +890,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
static void setup_uma_memory(void)
{
#if CONFIG_GFXUMA
#if IS_ENABLED(CONFIG_GFXUMA)
uint32_t topmem = (uint32_t) bsp_topmem();
uma_memory_size = get_uma_memory_size(topmem);
uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */
@ -989,7 +989,7 @@ static void amdfam10_domain_set_resources(device_t dev)
i, mmio_basek, basek, limitk);
}
#if CONFIG_GFXUMA
#if IS_ENABLED(CONFIG_GFXUMA)
uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10);
#endif
@ -1330,7 +1330,7 @@ static struct device_operations pci_domain_ops = {
#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
.acpi_name = amdfam10_domain_acpi_name,
#endif
#if CONFIG_GENERATE_SMBIOS_TABLES
#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES)
.get_smbios_data = amdfam10_get_smbios_data,
#endif
};
@ -1359,7 +1359,7 @@ static void sysconf_init(device_t dev) // first node
sysconf.bsp_apicid = lapicid();
sysconf.apicid_offset = sysconf.bsp_apicid;
#if CONFIG_ENABLE_APIC_EXT_ID
#if IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID)
if (pci_read_config32(dev, 0x68) & (HTTC_APIC_EXT_ID|HTTC_APIC_EXT_BRD_CST))
{
sysconf.enabled_apic_ext_id = 1;
@ -1454,7 +1454,7 @@ static void cpu_bus_scan(device_t dev)
}
disable_siblings = !CONFIG_LOGICAL_CPUS;
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
get_option(&disable_siblings, "multi_core");
#endif
@ -1659,7 +1659,7 @@ static void cpu_bus_scan(device_t dev)
}
}
#if CONFIG_ENABLE_APIC_EXT_ID && (CONFIG_APIC_ID_OFFSET > 0)
#if IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)
if (sysconf.enabled_apic_ext_id) {
if (apic_id != 0 || sysconf.lift_bsp_apicid) {
apic_id += sysconf.apicid_offset;
@ -1948,7 +1948,7 @@ static void cpu_bus_init(device_t dev)
detect_and_enable_probe_filter(dev);
detect_and_enable_cache_partitioning(dev);
initialize_cpus(dev->link_list);
#if CONFIG_AMD_SB_CIMX
#if IS_ENABLED(CONFIG_AMD_SB_CIMX)
sb_After_Pci_Init();
sb_Mid_Post_Init();
#endif

4
src/northbridge/amd/amdht/h3finit.c
View file

@ -1492,13 +1492,13 @@ static void selectOptimalWidthAndFrequency(sMainData *pDat)
cbPCBFreqLimit = ht_speed_mhz_to_hw(pDat->HtBlock->ht_link_configuration->ht_speed_limit);
cbPCBFreqLimit = min(cbPCBFreqLimit, cbPCBFreqLimit_NVRAM);
#if CONFIG_LIMIT_HT_DOWN_WIDTH_8
#if IS_ENABLED(CONFIG_LIMIT_HT_DOWN_WIDTH_8)
cbPCBABDownstreamWidth = 8;
#else
cbPCBABDownstreamWidth = 16;
#endif
#if CONFIG_LIMIT_HT_UP_WIDTH_8
#if IS_ENABLED(CONFIG_LIMIT_HT_UP_WIDTH_8)
cbPCBBAUpstreamWidth = 8;
#else
cbPCBBAUpstreamWidth = 16;

2
src/northbridge/amd/amdk8/Makefile.inc
View file

@ -20,7 +20,7 @@ romstage-y += coherent_ht.c
# Not sure what to do with these yet. How did raminit_test even work?
# Should be a target in -y form.
#if CONFIG_K8_REV_F_SUPPORT
#if IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)
#
#makerule raminit_test
# depends "$(TOP)/src/northbridge/amd/amdk8/raminit_test.c"

4
src/northbridge/amd/amdk8/amdk8.h
View file

@ -2,7 +2,7 @@
#define AMDK8_H
#if CONFIG_K8_REV_F_SUPPORT
#if IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@ -26,7 +26,7 @@ void setup_resource_map_offset(const unsigned int *register_values, int max, uns
void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, const uint16_t *spd_addr);
int optimize_link_coherent_ht(void);
unsigned int get_nodes(void);
#if CONFIG_RAMINIT_SYSINFO
#if IS_ENABLED(CONFIG_RAMINIT_SYSINFO)
void setup_coherent_ht_domain(void);
#else
int setup_coherent_ht_domain(void);

28
src/northbridge/amd/amdk8/coherent_ht.c
View file

@ -73,7 +73,7 @@
#include <stdint.h>
#include <arch/io.h>
#include <pc80/mc146818rtc.h>
#if CONFIG_HAVE_OPTION_TABLE
#if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE)
#include "option_table.h"
#endif
@ -258,8 +258,8 @@ static uint16_t read_freq_cap(pci_devfn_t dev, uint8_t pos)
freq_cap = pci_read_config16(dev, pos);
freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */
#if CONFIG_K8_HT_FREQ_1G_SUPPORT
#if !CONFIG_K8_REV_F_SUPPORT
#if IS_ENABLED(CONFIG_K8_HT_FREQ_1G_SUPPORT)
#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)
if (!is_cpu_pre_e0())
#endif
{
@ -633,7 +633,7 @@ static void setup_remote_row_indirect_group(const u8 *conn, int num)
static void setup_uniprocessor(void)
{
printk(BIOS_SPEW, "Enabling UP settings\n");
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
unsigned tmp = (pci_read_config32(NODE_MC(0), 0xe8) >> 12) & 3;
if (tmp > 0) return;
#endif
@ -1516,7 +1516,7 @@ static void clear_dead_routes(unsigned nodes)
}
#endif /* CONFIG_MAX_PHYSICAL_CPUS > 1 */
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
static unsigned verify_dualcore(unsigned nodes)
{
unsigned node, totalcpus, tmp;
@ -1535,10 +1535,10 @@ static unsigned verify_dualcore(unsigned nodes)
static void coherent_ht_finalize(unsigned nodes)
{
unsigned node;
#if !CONFIG_K8_REV_F_SUPPORT
#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)
int rev_a0;
#endif
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
unsigned total_cpus;
if (read_option(multi_core, 0) == 0) { /* multi_core */
@ -1556,7 +1556,7 @@ static void coherent_ht_finalize(unsigned nodes)
*/
printk(BIOS_SPEW, "coherent_ht_finalize\n");
#if !CONFIG_K8_REV_F_SUPPORT
#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)
rev_a0 = is_cpu_rev_a0();
#endif
for (node = 0; node < nodes; node++) {
@ -1567,7 +1567,7 @@ static void coherent_ht_finalize(unsigned nodes)
/* Set the Total CPU and Node count in the system */
val = pci_read_config32(dev, 0x60);
val &= (~0x000F0070);
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
val |= ((total_cpus-1)<<16)|((nodes-1)<<4);
#else
val |= ((nodes-1)<<16)|((nodes-1)<<4);
@ -1587,7 +1587,7 @@ static void coherent_ht_finalize(unsigned nodes)
(3 << HTTC_HI_PRI_BYP_CNT_SHIFT);
pci_write_config32(dev, HT_TRANSACTION_CONTROL, val);
#if !CONFIG_K8_REV_F_SUPPORT
#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)
if (rev_a0) {
pci_write_config32(dev, 0x94, 0);
pci_write_config32(dev, 0xb4, 0);
@ -1607,7 +1607,7 @@ static int apply_cpu_errata_fixes(unsigned nodes)
pci_devfn_t dev;
uint32_t cmd;
dev = NODE_MC(node);
#if !CONFIG_K8_REV_F_SUPPORT
#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)
if (is_cpu_pre_c0()) {
/* Errata 66
@ -1652,7 +1652,7 @@ static int apply_cpu_errata_fixes(unsigned nodes)
#endif
#if !CONFIG_K8_REV_F_SUPPORT
#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)
/* I can't touch this msr on early buggy cpus, and cannot apply either 169 or 131 */
if (!is_cpu_pre_b3())
#endif
@ -1770,7 +1770,7 @@ int optimize_link_coherent_ht(void)
return needs_reset;
}
#if CONFIG_RAMINIT_SYSINFO
#if IS_ENABLED(CONFIG_RAMINIT_SYSINFO)
void setup_coherent_ht_domain(void)
#else
int setup_coherent_ht_domain(void)
@ -1792,7 +1792,7 @@ int setup_coherent_ht_domain(void)
}
coherent_ht_finalize(nodes);
#if !CONFIG_RAMINIT_SYSINFO
#if !IS_ENABLED(CONFIG_RAMINIT_SYSINFO)
return optimize_link_coherent_ht();
#endif
}

6
src/northbridge/amd/amdk8/debug.c
View file

@ -12,7 +12,7 @@
void print_debug_addr(const char *str, void *val)
{
#if CONFIG_DEBUG_CAR
#if IS_ENABLED(CONFIG_DEBUG_CAR)
printk(BIOS_DEBUG, "------Address debug: %s%p------\n", str, val);
#endif
}
@ -64,7 +64,7 @@ void dump_pci_device(unsigned dev)
printk(BIOS_DEBUG, "\n");
}
#if CONFIG_K8_REV_F_SUPPORT
#if IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)
void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg)
{
int i;
@ -136,7 +136,7 @@ void dump_pci_devices_on_bus(unsigned busn)
}
}
#if CONFIG_DEBUG_SMBUS
#if IS_ENABLED(CONFIG_DEBUG_SMBUS)
void dump_spd_registers(const struct mem_controller *ctrl)
{

44
src/northbridge/amd/amdk8/incoherent_ht.c
View file

@ -131,8 +131,8 @@ static uint16_t ht_read_freq_cap(pci_devfn_t dev, uint8_t pos)
/* AMD K8 Unsupported 1GHz? */
if (id == (PCI_VENDOR_ID_AMD | (0x1100 << 16))) {
#if CONFIG_K8_HT_FREQ_1G_SUPPORT
#if !CONFIG_K8_REV_F_SUPPORT
#if IS_ENABLED(CONFIG_K8_HT_FREQ_1G_SUPPORT)
#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)
if (is_cpu_pre_e0()) { // only E0 later support 1GHz
freq_cap &= ~(1 << HT_FREQ_1000Mhz);
}
@ -144,7 +144,7 @@ static uint16_t ht_read_freq_cap(pci_devfn_t dev, uint8_t pos)
printk(BIOS_SPEW, "pos=0x%x, filtered freq_cap=0x%x\n", pos, freq_cap);
#if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M890
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M890)
freq_cap &= 0x3f;
printk(BIOS_INFO, "Limiting HT to 800/600/400/200 MHz until K8M890 HT1000 is fixed.\n");
#endif
@ -283,7 +283,7 @@ static int ht_optimize_link(
return needs_reset;
}
#if CONFIG_RAMINIT_SYSINFO
#if IS_ENABLED(CONFIG_RAMINIT_SYSINFO)
static void ht_setup_chainx(pci_devfn_t udev, uint8_t upos, uint8_t bus,
unsigned offset_unitid, struct sys_info *sysinfo)
#else
@ -296,7 +296,7 @@ static int ht_setup_chainx(pci_devfn_t udev, uint8_t upos, uint8_t bus,
uint8_t next_unitid, last_unitid;
unsigned uoffs;
#if !CONFIG_RAMINIT_SYSINFO
#if !IS_ENABLED(CONFIG_RAMINIT_SYSINFO)
int reset_needed = 0;
#endif
@ -403,7 +403,7 @@ static int ht_setup_chainx(pci_devfn_t udev, uint8_t upos, uint8_t bus,
flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
offs = ((flags>>10) & 1) ? PCI_HT_SLAVE1_OFFS : PCI_HT_SLAVE0_OFFS;
#if CONFIG_RAMINIT_SYSINFO
#if IS_ENABLED(CONFIG_RAMINIT_SYSINFO)
/* store the link pair here and we will Setup the Hypertransport link later, after we get final FID/VID */
{
struct link_pair_st *link_pair = &sysinfo->link_pair[sysinfo->link_pair_num];
@ -439,7 +439,7 @@ end_of_chain:;
flags |= CONFIG_HT_CHAIN_END_UNITID_BASE & 0x1f;
pci_write_config16(PCI_DEV(bus, real_last_unitid, 0), real_last_pos + PCI_CAP_FLAGS, flags);
#if CONFIG_RAMINIT_SYSINFO
#if IS_ENABLED(CONFIG_RAMINIT_SYSINFO)
// Here need to change the dev in the array
int i;
for (i = 0; i < sysinfo->link_pair_num; i++)
@ -458,7 +458,7 @@ end_of_chain:;
}
#endif
#if !CONFIG_RAMINIT_SYSINFO
#if !IS_ENABLED(CONFIG_RAMINIT_SYSINFO)
return reset_needed;
#endif
@ -527,7 +527,7 @@ static int optimize_link_read_pointers_chain(uint8_t ht_c_num)
return reset_needed;
}
#if CONFIG_SOUTHBRIDGE_NVIDIA_CK804 // || CONFIG_SOUTHBRIDGE_NVIDIA_MCP55
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_NVIDIA_CK804)
static int set_ht_link_buffer_count(uint8_t node, uint8_t linkn, uint8_t linkt, unsigned val)
{
uint32_t dword;
@ -587,7 +587,7 @@ static int set_ht_link_buffer_counts_chain(uint8_t ht_c_num, unsigned vendorid,
}
#endif
#if CONFIG_RAMINIT_SYSINFO
#if IS_ENABLED(CONFIG_RAMINIT_SYSINFO)
static void ht_setup_chains(uint8_t ht_c_num, struct sys_info *sysinfo)
#else
static int ht_setup_chains(uint8_t ht_c_num)
@ -602,7 +602,7 @@ static int ht_setup_chains(uint8_t ht_c_num)
pci_devfn_t udev;
uint8_t i;
#if !CONFIG_RAMINIT_SYSINFO
#if !IS_ENABLED(CONFIG_RAMINIT_SYSINFO)
int reset_needed = 0;
#else
sysinfo->link_pair_num = 0;
@ -634,7 +634,7 @@ static int ht_setup_chains(uint8_t ht_c_num)
upos = ((reg & 0xf00)>>8) * 0x20 + 0x80;
udev = PCI_DEV(0, devpos, 0);
#if CONFIG_RAMINIT_SYSINFO
#if IS_ENABLED(CONFIG_RAMINIT_SYSINFO)
ht_setup_chainx(udev,upos,busn, offset_unit_id(i == 0), sysinfo); // all not
#else
reset_needed |= ht_setup_chainx(udev,upos,busn, offset_unit_id(i == 0)); //all not
@ -642,7 +642,7 @@ static int ht_setup_chains(uint8_t ht_c_num)
}
#if !CONFIG_RAMINIT_SYSINFO
#if !IS_ENABLED(CONFIG_RAMINIT_SYSINFO)
reset_needed |= optimize_link_read_pointers_chain(ht_c_num);
return reset_needed;
@ -650,7 +650,7 @@ static int ht_setup_chains(uint8_t ht_c_num)
}
#if CONFIG_RAMINIT_SYSINFO
#if IS_ENABLED(CONFIG_RAMINIT_SYSINFO)
static void ht_setup_chains_x(struct sys_info *sysinfo)
#else
static int ht_setup_chains_x(void)
@ -662,7 +662,7 @@ static int ht_setup_chains_x(void)
uint8_t next_busn;
uint8_t ht_c_num;
uint8_t nodes;
#if CONFIG_K8_ALLOCATE_IO_RANGE
#if IS_ENABLED(CONFIG_K8_ALLOCATE_IO_RANGE)
unsigned next_io_base;
#endif
@ -672,7 +672,7 @@ static int ht_setup_chains_x(void)
reg = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64);
/* update PCI_DEV(0, 0x18, 1) 0xe0 to 0x05000m03, and next_busn = 0x3f+1 */
print_linkn_in("SBLink=", ((reg>>8) & 3));
#if CONFIG_RAMINIT_SYSINFO
#if IS_ENABLED(CONFIG_RAMINIT_SYSINFO)
sysinfo->sblk = (reg>>8) & 3;
sysinfo->sbbusn = 0;
sysinfo->nodes = nodes;
@ -682,7 +682,7 @@ static int ht_setup_chains_x(void)
next_busn = 0x3f+1; /* 0 will be used ht chain with SB we need to keep SB in bus0 in auto stage*/
#if CONFIG_K8_ALLOCATE_IO_RANGE
#if IS_ENABLED(CONFIG_K8_ALLOCATE_IO_RANGE)
/* io range allocation */
tempreg = 0 | (((reg>>8) & 0x3) << 4)| (0x3<<12); //limit
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC4, tempreg);
@ -695,7 +695,7 @@ static int ht_setup_chains_x(void)
for (ht_c_num = 1;ht_c_num < 4; ht_c_num++) {
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4, 0);
#if CONFIG_K8_ALLOCATE_IO_RANGE
#if IS_ENABLED(CONFIG_K8_ALLOCATE_IO_RANGE)
/* io range allocation */
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xc4 + ht_c_num * 8, 0);
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xc0 + ht_c_num * 8, 0);
@ -728,7 +728,7 @@ static int ht_setup_chains_x(void)
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4, tempreg);
next_busn+=0x3f+1;
#if CONFIG_K8_ALLOCATE_IO_RANGE
#if IS_ENABLED(CONFIG_K8_ALLOCATE_IO_RANGE)
/* io range allocation */
tempreg = nodeid | (linkn<<4) | ((next_io_base+0x3)<<12); //limit
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC4 + ht_c_num * 8, tempreg);
@ -752,7 +752,7 @@ static int ht_setup_chains_x(void)
pci_write_config32(dev, regpos, reg);
}
#if CONFIG_K8_ALLOCATE_IO_RANGE
#if IS_ENABLED(CONFIG_K8_ALLOCATE_IO_RANGE)
/* io range allocation */
for (i = 0; i < 4; i++) {
unsigned regpos;
@ -778,7 +778,7 @@ static int ht_setup_chains_x(void)
}
}
#if CONFIG_RAMINIT_SYSINFO
#if IS_ENABLED(CONFIG_RAMINIT_SYSINFO)
sysinfo->ht_c_num = i;
ht_setup_chains(i, sysinfo);
sysinfo->sbdn = get_sbdn(sysinfo->sbbusn);
@ -788,7 +788,7 @@ static int ht_setup_chains_x(void)
}
#if CONFIG_RAMINIT_SYSINFO
#if IS_ENABLED(CONFIG_RAMINIT_SYSINFO)
static int optimize_link_incoherent_ht(struct sys_info *sysinfo)
{
// We need to use recorded link pair info to optimize the link

2
src/northbridge/amd/amdk8/misc_control.c
View file

@ -121,7 +121,7 @@ static void misc_control_init(struct device *dev)
cmd = pci_read_config32(dev, 0x44);
cmd |= (1<<6) | (1<<25);
pci_write_config32(dev, 0x44, cmd);
#if !CONFIG_K8_REV_F_SUPPORT
#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)
if (is_cpu_pre_c0()) {
/* Errata 58

27
src/northbridge/amd/amdk8/northbridge.c
View file

@ -25,7 +25,7 @@
#include <cpu/amd/mtrr.h>
#include <cpu/amd/multicore.h>
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
#include <pc80/mc146818rtc.h>
#endif
@ -484,7 +484,7 @@ static void amdk8_create_vga_resource(device_t dev, unsigned nodeid)
* we only deal with the 'first' vga card */
for (link = dev->link_list; link; link = link->next) {
if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
#if CONFIG_MULTIPLE_VGA_ADAPTERS
#if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)
extern device_t vga_pri; // the primary vga device, defined in device.c
printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d link bus range [%d,%d]\n", vga_pri->bus->secondary,
link->secondary,link->subordinate);
@ -811,10 +811,11 @@ static u32 hoist_memory(unsigned long hole_startk, int node_id)
static void setup_uma_memory(void)
{
#if CONFIG_GFXUMA
#if IS_ENABLED(CONFIG_GFXUMA)
uint32_t topmem = (uint32_t) bsp_topmem();
#if !CONFIG_BOARD_ASROCK_939A785GMH && !CONFIG_BOARD_AMD_MAHOGANY
#if !IS_ENABLED(CONFIG_BOARD_ASROCK_939A785GMH) && \
!IS_ENABLED(CONFIG_BOARD_AMD_MAHOGANY)
switch (topmem) {
case 0x10000000: /* 256M system memory */
@ -885,7 +886,7 @@ static void amdk8_domain_set_resources(device_t dev)
* if mmio_basek is bigger that hole_basek and will use hole_basek as mmio_basek and we don't need to reset hole.
* otherwise We reset the hole to the mmio_basek
*/
#if !CONFIG_K8_REV_F_SUPPORT
#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)
if (!is_cpu_pre_e0()) {
#endif
@ -903,7 +904,7 @@ static void amdk8_domain_set_resources(device_t dev)
disable_hoist_memory(mem_hole.hole_startk, mem_hole.node_id);
}
#if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
#if IS_ENABLED(CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC)
//We need to double check if the mmio_basek is valid for hole setting, if it is equal to basek, we need to decrease it some
u32 basek_pri;
for (i = 0; i < fx_devs; i++) {
@ -924,7 +925,7 @@ static void amdk8_domain_set_resources(device_t dev)
#endif
}
#if !CONFIG_K8_REV_F_SUPPORT
#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)
} // is_cpu_pre_e0
#endif
@ -953,7 +954,7 @@ static void amdk8_domain_set_resources(device_t dev)
}
#if CONFIG_GFXUMA
#if IS_ENABLED(CONFIG_GFXUMA)
printk(BIOS_DEBUG, "node %d : uma_memory_base/1024=0x%08llx, mmio_basek=0x%08lx, basek=0x%08x, limitk=0x%08x\n", i, uma_memory_base >> 10, mmio_basek, basek, limitk);
if ((uma_memory_base >> 10) < mmio_basek)
printk(BIOS_ALERT, "node %d: UMA memory starts below mmio_basek\n", i);
@ -973,7 +974,7 @@ static void amdk8_domain_set_resources(device_t dev)
}
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
if (reset_memhole)
#if !CONFIG_K8_REV_F_SUPPORT
#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)
if (!is_cpu_pre_e0())
#endif
sizek += hoist_memory(mmio_basek,i);
@ -998,7 +999,7 @@ static void amdk8_domain_set_resources(device_t dev)
ramtop = limitk * 1024;
}
#if CONFIG_GFXUMA
#if IS_ENABLED(CONFIG_GFXUMA)
set_late_cbmem_top(uma_memory_base);
uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10);
#else
@ -1128,7 +1129,7 @@ static void cpu_bus_scan(device_t dev)
sysconf.apicid_offset = bsp_apicid;
disable_siblings = !CONFIG_LOGICAL_CPUS;
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
get_option(&disable_siblings, "multi_core");
#endif
@ -1201,7 +1202,7 @@ static void cpu_bus_scan(device_t dev)
// That is the typical case
if (j == 0) {
#if !CONFIG_K8_REV_F_SUPPORT
#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)
e0_later_single_core = is_e0_later_in_bsp(i); // single core
#else
e0_later_single_core = is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3
@ -1250,7 +1251,7 @@ static void cpu_bus_scan(device_t dev)
static void cpu_bus_init(device_t dev)
{
#if CONFIG_WAIT_BEFORE_CPUS_INIT
#if IS_ENABLED(CONFIG_WAIT_BEFORE_CPUS_INIT)
cpus_ready_for_init();
#endif
initialize_cpus(dev->link_list);

42
src/northbridge/amd/amdk8/raminit.c
View file

@ -15,7 +15,7 @@
#include <reset.h>
#include "raminit.h"
#include "amdk8.h"
#if CONFIG_HAVE_OPTION_TABLE
#if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE)
#include "option_table.h"
#endif
@ -43,7 +43,7 @@ static int controller_present(const struct mem_controller *ctrl)
return pci_read_config32(ctrl->f0, 0) == 0x11001022;
}
#if CONFIG_RAMINIT_SYSINFO
#if IS_ENABLED(CONFIG_RAMINIT_SYSINFO)
void sdram_set_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo)
#else
void sdram_set_registers(const struct mem_controller *ctrl)
@ -592,7 +592,7 @@ struct dimm_size {
unsigned long side2;
unsigned long rows;
unsigned long col;
#if CONFIG_QRANK_DIMM_SUPPORT
#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)
unsigned long rank;
#endif
};
@ -606,7 +606,7 @@ static struct dimm_size spd_get_dimm_size(unsigned device)
sz.side2 = 0;
sz.rows = 0;
sz.col = 0;
#if CONFIG_QRANK_DIMM_SUPPORT
#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)
sz.rank = 0;
#endif
@ -650,7 +650,7 @@ static struct dimm_size spd_get_dimm_size(unsigned device)
if ((value != 2) && (value != 4)) {
goto val_err;
}
#if CONFIG_QRANK_DIMM_SUPPORT
#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)
sz.rank = value;
#endif
@ -679,7 +679,7 @@ hw_err:
sz.side2 = 0;
sz.rows = 0;
sz.col = 0;
#if CONFIG_QRANK_DIMM_SUPPORT
#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)
sz.rank = 0;
#endif
out:
@ -727,7 +727,7 @@ static void set_dimm_size(const struct mem_controller *ctrl, struct dimm_size sz
/* Set the appropriate DIMM base address register */
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), base0);
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), base1);
#if CONFIG_QRANK_DIMM_SUPPORT
#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)
if (sz.rank == 4) {
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+4)<<2), base0);
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+5)<<2), base1);
@ -738,7 +738,7 @@ static void set_dimm_size(const struct mem_controller *ctrl, struct dimm_size sz
if (base0) {
dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
dch |= DCH_MEMCLK_EN0 << index;
#if CONFIG_QRANK_DIMM_SUPPORT
#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)
if (sz.rank == 4) {
dch |= DCH_MEMCLK_EN0 << (index + 2);
}
@ -760,7 +760,7 @@ static void set_dimm_map(const struct mem_controller *ctrl, struct dimm_size sz,
map = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);
map &= ~(0xf << (index * 4));
#if CONFIG_QRANK_DIMM_SUPPORT
#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)
if (sz.rank == 4) {
map &= ~(0xf << ((index + 2) * 4));
}
@ -771,7 +771,7 @@ static void set_dimm_map(const struct mem_controller *ctrl, struct dimm_size sz,
if (sz.side1 >= (25 +3)) {
if (is_cpu_pre_d0()) {
map |= (sz.side1 - (25 + 3)) << (index *4);
#if CONFIG_QRANK_DIMM_SUPPORT
#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)
if (sz.rank == 4) {
map |= (sz.side1 - (25 + 3)) << ((index + 2) * 4);
}
@ -779,7 +779,7 @@ static void set_dimm_map(const struct mem_controller *ctrl, struct dimm_size sz,
}
else {
map |= cs_map_aa[(sz.rows - 12) * 5 + (sz.col - 8) ] << (index*4);
#if CONFIG_QRANK_DIMM_SUPPORT
#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)
if (sz.rank == 4) {
map |= cs_map_aa[(sz.rows - 12) * 5 + (sz.col - 8) ] << ((index + 2) * 4);
}
@ -1164,7 +1164,7 @@ static long spd_handle_unbuffered_dimms(const struct mem_controller *ctrl,
if (unbuffered) {
if ((has_dualch) && (!is_cpu_pre_d0())) {
dcl |= DCL_UnBuffDimm;
#if CONFIG_CPU_AMD_SOCKET_939
#if IS_ENABLED(CONFIG_CPU_AMD_SOCKET_939)
if ((cpuid_eax(1) & 0x30) == 0x30) {
/* CS[7:4] is copy of CS[3:0], should be set for 939 socket */
dcl |= DCL_UpperCSMap;
@ -1375,7 +1375,7 @@ struct spd_set_memclk_result {
static int spd_dimm_loading_socket(const struct mem_controller *ctrl, long dimm_mask, int *freq_1t)
{
#if CONFIG_CPU_AMD_SOCKET_939
#if IS_ENABLED(CONFIG_CPU_AMD_SOCKET_939)
/* + 1 raise so we detect 0 as bad field */
#define DDR200 (NBCAP_MEMCLK_100MHZ + 1)
@ -1488,7 +1488,7 @@ hw_error:
return NBCAP_MEMCLK_200MHZ;
}
#elif CONFIG_CPU_AMD_SOCKET_754
#elif IS_ENABLED(CONFIG_CPU_AMD_SOCKET_754)
#define CFGIDX(DIMM1,DIMM2,DIMM3) ((DIMM3)*9+(DIMM2)*3+(DIMM1))
@ -1657,7 +1657,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
if (freq == sizeof(cl_at_freq))
goto hw_error;
#if CONFIG_CPU_AMD_SOCKET_754
#if IS_ENABLED(CONFIG_CPU_AMD_SOCKET_754)
if (freq < max_freq_1t || CONFIG_K8_FORCE_2T_DRAM_TIMING) {
pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW,
pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW) | DCL_En2T);
@ -1899,7 +1899,7 @@ static int update_dimm_x4(const struct mem_controller *ctrl, const struct mem_pa
{
uint32_t dcl;
int value;
#if CONFIG_QRANK_DIMM_SUPPORT
#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)
int rank;
#endif
int dimm;
@ -1908,7 +1908,7 @@ static int update_dimm_x4(const struct mem_controller *ctrl, const struct mem_pa
return -1;
}
#if CONFIG_QRANK_DIMM_SUPPORT
#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)
rank = spd_read_byte(ctrl->channel0[i], 5); /* number of physical banks */
if (rank < 0) {
return -1;
@ -1916,7 +1916,7 @@ static int update_dimm_x4(const struct mem_controller *ctrl, const struct mem_pa
#endif
dimm = 1<<(DCL_x4DIMM_SHIFT+i);
#if CONFIG_QRANK_DIMM_SUPPORT
#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)
if (rank == 4) {
dimm |= 1<<(DCL_x4DIMM_SHIFT+i+2);
}
@ -2168,7 +2168,7 @@ static long spd_set_dram_timing(const struct mem_controller *ctrl, const struct
return dimm_mask;
}
#if CONFIG_RAMINIT_SYSINFO
#if IS_ENABLED(CONFIG_RAMINIT_SYSINFO)
void sdram_set_spd_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo)
#else
void sdram_set_spd_registers(const struct mem_controller *ctrl)
@ -2277,7 +2277,7 @@ void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl)
hole_startk = 4*1024*1024 - CONFIG_HW_MEM_HOLE_SIZEK;
printk(BIOS_SPEW, "Handling memory hole at 0x%08x (default)\n", hole_startk);
#if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
#if IS_ENABLED(CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC)
/* We need to double check if hole_startk is valid.
* If it is equal to the dram base address in K (base_k),
* we need to decrease it.
@ -2327,7 +2327,7 @@ void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl)
#endif
#if CONFIG_RAMINIT_SYSINFO
#if IS_ENABLED(CONFIG_RAMINIT_SYSINFO)
void sdram_enable(int controllers, const struct mem_controller *ctrl, struct sys_info *sysinfo)
#else
void sdram_enable(int controllers, const struct mem_controller *ctrl)

2
src/northbridge/amd/amdk8/raminit.h
View file

@ -26,7 +26,7 @@ void set_sysinfo_in_ram(unsigned int val);
#define TIMEOUT_LOOPS 300000
#if defined(__PRE_RAM__) && CONFIG_RAMINIT_SYSINFO
#if defined(__PRE_RAM__) && IS_ENABLED(CONFIG_RAMINIT_SYSINFO)
void sdram_initialize(int controllers, const struct mem_controller *ctrl, void *sysinfo);
void sdram_enable(int controllers, const struct mem_controller *ctrl,
struct sys_info *sysinfo);

30
src/northbridge/amd/amdk8/raminit_f.c
View file

@ -33,11 +33,11 @@
#include "raminit.h"
#include "f.h"
#include <spd_ddr2.h>
#if CONFIG_HAVE_OPTION_TABLE
#if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE)
#include "option_table.h"
#endif
#if CONFIG_DEBUG_RAM_SETUP
#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
#define printk_raminit(args...) printk(BIOS_DEBUG, args)
#else
#define printk_raminit(args...)
@ -845,7 +845,7 @@ static void set_dimm_size(const struct mem_controller *ctrl,
/* Set the appropriate DIMM base address register */
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 0) << 2), base0);
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 1) << 2), base1);
#if CONFIG_QRANK_DIMM_SUPPORT
#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)
if (sz->rank == 4) {
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), base0);
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), base1);
@ -873,7 +873,7 @@ static void set_dimm_size(const struct mem_controller *ctrl,
} else {
dword = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); //Channel A
dword &= ~(ClkDis0 >> index);
#if CONFIG_QRANK_DIMM_SUPPORT
#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)
if (sz->rank == 4) {
dword &= ~(ClkDis0 >> (index+2));
}
@ -883,7 +883,7 @@ static void set_dimm_size(const struct mem_controller *ctrl,
if (meminfo->is_Width128) { // ChannelA+B
dword = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC);
dword &= ~(ClkDis0 >> index);
#if CONFIG_QRANK_DIMM_SUPPORT
#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)
if (sz->rank == 4) {
dword &= ~(ClkDis0 >> (index+2));
}
@ -936,7 +936,7 @@ static void set_dimm_cs_map(const struct mem_controller *ctrl,
}
map = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);
map &= ~(0xf << (index * 4));
#if CONFIG_QRANK_DIMM_SUPPORT
#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)
if (sz->rank == 4) {
map &= ~(0xf << ((index + 2) * 4));
}
@ -947,7 +947,7 @@ static void set_dimm_cs_map(const struct mem_controller *ctrl,
unsigned temp_map;
temp_map = cs_map_aaa[(sz->bank-2)*3*4 + (sz->rows - 13)*3 + (sz->col - 9) ];
map |= temp_map << (index*4);
#if CONFIG_QRANK_DIMM_SUPPORT
#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)
if (sz->rank == 4) {
map |= temp_map << ((index + 2) * 4);
}
@ -1291,7 +1291,7 @@ static long disable_dimm(const struct mem_controller *ctrl, unsigned index,
} else {
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 0) << 2), 0);
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 1) << 2), 0);
#if CONFIG_QRANK_DIMM_SUPPORT
#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)
if (meminfo->sz[index].rank == 4) {
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), 0);
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), 0);
@ -2173,7 +2173,7 @@ static int update_dimm_Tref(const struct mem_controller *ctrl,
static void set_4RankRDimm(const struct mem_controller *ctrl,
const struct mem_param *param, struct mem_info *meminfo)
{
#if CONFIG_QRANK_DIMM_SUPPORT
#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)
int value;
int i;
long dimm_mask = meminfo->dimm_mask;
@ -2213,7 +2213,7 @@ static uint32_t get_extra_dimm_mask(const struct mem_controller *ctrl,
uint32_t mask_single_rank;
uint32_t mask_page_1k;
int value;
#if CONFIG_QRANK_DIMM_SUPPORT
#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)
int rank;
#endif
@ -2246,20 +2246,20 @@ static uint32_t get_extra_dimm_mask(const struct mem_controller *ctrl,
value = spd_read_byte(spd_device, SPD_PRI_WIDTH);
#if CONFIG_QRANK_DIMM_SUPPORT
#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)
rank = meminfo->sz[i].rank;
#endif
if (value == 4) {
mask_x4 |= (1<<i);
#if CONFIG_QRANK_DIMM_SUPPORT
#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)
if (rank == 4) {
mask_x4 |= 1<<(i+2);
}
#endif
} else if (value == 16) {
mask_x16 |= (1<<i);
#if CONFIG_QRANK_DIMM_SUPPORT
#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)
if (rank == 4) {
mask_x16 |= 1<<(i+2);
}
@ -2348,7 +2348,7 @@ static void set_ecc(const struct mem_controller *ctrl,
dcl &= ~DCL_DimmEccEn;
}
#else // CMOS_VSTART_ECC_memory not defined
#if !CONFIG_ECC_MEMORY
#if !IS_ENABLED(CONFIG_ECC_MEMORY)
dcl &= ~DCL_DimmEccEn;
#endif
#endif
@ -2932,7 +2932,7 @@ void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl)
hole_startk = 4*1024*1024 - CONFIG_HW_MEM_HOLE_SIZEK;
printk_raminit("Handling memory hole at 0x%08x (default)\n", hole_startk);
#if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
#if IS_ENABLED(CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC)
/* We need to double check if the hole_startk is valid, if it is equal
to basek, we need to decrease it some */
uint32_t basek_pri;

4
src/northbridge/amd/amdk8/raminit_f_dqs.c
View file

@ -1782,7 +1782,7 @@ void set_sysinfo_in_ram(unsigned val)
#endif
}
#if CONFIG_HAVE_ACPI_RESUME
#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
#if CONFIG_MEM_TRAIN_SEQ == 0
static int save_index_to_pos(unsigned int dev, int size, int index, int nvram_pos)
@ -1937,7 +1937,7 @@ static void dqs_timing(int controllers, const struct mem_controller *ctrl, struc
if (train_DqsRcvrEn(ctrl+i, 2, sysinfo)) goto out;
printk(BIOS_DEBUG, " done\n");
sysinfo->mem_trained[i]=1;
#if CONFIG_HAVE_ACPI_RESUME
#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
dqs_save_MC_NVRAM((ctrl+i)->f2);
#endif
}

16
src/northbridge/amd/amdmct/wrappers/mcti_d.c
View file

@ -128,16 +128,16 @@ u16 mctGet_NVbits(u8 index)
//val = 2; /* S4 (Unbuffered SO-DIMMS) */
break;
case NV_BYPMAX:
#if !CONFIG_GFXUMA
#if !IS_ENABLED(CONFIG_GFXUMA)
val = 4;
#elif CONFIG_GFXUMA
#elif IS_ENABLED(CONFIG_GFXUMA)
val = 7;
#endif
break;
case NV_RDWRQBYP:
#if !CONFIG_GFXUMA
#if !IS_ENABLED(CONFIG_GFXUMA)
val = 2;
#elif CONFIG_GFXUMA
#elif IS_ENABLED(CONFIG_GFXUMA)
val = 3;
#endif
break;
@ -191,9 +191,9 @@ u16 mctGet_NVbits(u8 index)
val = !!nvram;
break;
case NV_BurstLen32:
#if !CONFIG_GFXUMA
#if !IS_ENABLED(CONFIG_GFXUMA)
val = 0; /* 64 byte mode */
#elif CONFIG_GFXUMA
#elif IS_ENABLED(CONFIG_GFXUMA)
val = 1; /* 32 byte mode */
#endif
break;
@ -212,9 +212,9 @@ u16 mctGet_NVbits(u8 index)
case NV_BottomIO:
case NV_BottomUMA:
/* address bits [31:24] */
#if !CONFIG_GFXUMA
#if !IS_ENABLED(CONFIG_GFXUMA)
val = (CONFIG_MMCONF_BASE_ADDRESS >> 24);
#elif CONFIG_GFXUMA
#elif IS_ENABLED(CONFIG_GFXUMA)
#if (CONFIG_MMCONF_BASE_ADDRESS < (MAXIMUM_GFXUMA_SIZE + MINIMUM_DRAM_BELOW_4G))
#error "MMCONF_BASE_ADDRESS is too small"
#endif

2
src/northbridge/amd/cimx/rd890/NbPlatform.h
View file

@ -26,7 +26,7 @@
#ifdef CIMX_TRACE_SUPPORT
#define CIMX_INIT_TRACE(Arguments)
#if CONFIG_REDIRECT_NBCIMX_TRACE_TO_SERIAL
#if IS_ENABLED(CONFIG_REDIRECT_NBCIMX_TRACE_TO_SERIAL)
#define TRACE_DATA(Ptr, Level) BIOS_DEBUG //always enable
#define CIMX_TRACE(Argument) do {do_printk Argument;} while (0)
#else

2
src/northbridge/amd/pi/00630F01/northbridge.c
View file

@ -46,7 +46,7 @@
#define MAX_NODE_NUMS (MAX_NODES * MAX_DIES)
#if (defined CONFIG_EXT_CONF_SUPPORT) && CONFIG_EXT_CONF_SUPPORT == 1
#if IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)
#error CONFIG_EXT_CONF_SUPPORT == 1 not support anymore!
#endif

4
src/northbridge/amd/pi/00660F01/northbridge.c
View file

@ -45,7 +45,7 @@
#define MAX_NODE_NUMS (MAX_NODES * MAX_DIES)
#if (defined CONFIG_EXT_CONF_SUPPORT) && CONFIG_EXT_CONF_SUPPORT == 1
#if IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)
#error CONFIG_EXT_CONF_SUPPORT == 1 not support anymore!
#endif
@ -381,7 +381,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid)
* we only deal with the 'first' vga card */
for (link = dev->link_list; link; link = link->next) {
if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
#if CONFIG_MULTIPLE_VGA_ADAPTERS
#if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)
extern device_t vga_pri; // the primary vga device, defined in device.c
printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
link->secondary,link->subordinate);

4
src/northbridge/amd/pi/00670F00/northbridge.c
View file

@ -45,7 +45,7 @@
#define MAX_NODE_NUMS (MAX_NODES * MAX_DIES)
#if (defined CONFIG_EXT_CONF_SUPPORT) && CONFIG_EXT_CONF_SUPPORT == 1
#if IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)
#error CONFIG_EXT_CONF_SUPPORT == 1 not support anymore!
#endif
@ -381,7 +381,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid)
* we only deal with the 'first' vga card */
for (link = dev->link_list; link; link = link->next) {
if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
#if CONFIG_MULTIPLE_VGA_ADAPTERS
#if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)
extern device_t vga_pri; // the primary vga device, defined in device.c
printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
link->secondary,link->subordinate);

2
src/northbridge/amd/pi/00730F01/northbridge.c
View file

@ -391,7 +391,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid)
* we only deal with the 'first' vga card */
for (link = dev->link_list; link; link = link->next) {
if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
#if CONFIG_MULTIPLE_VGA_ADAPTERS
#if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)
extern device_t vga_pri; // the primary vga device, defined in device.c
printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
link->secondary,link->subordinate);