From 77b36abcf6436734f74a40218b83fd82181ffb78 Mon Sep 17 00:00:00 2001
From: Tim Wawrzynczak <twawrzynczak@chromium.org>
Date: Thu, 1 Jul 2021 08:44:14 -0600
Subject: [PATCH] soc/intel/jasperlake: Switch to runtime generation of Intel
 Power Engine

The pep.asl file is being obsoleted by runtime generation, therefore
switch jasperlake boards to this method.

soc/intel/jasperlake: Switch to acpigen PEPD

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ib7f17f9b3b1396708ba68fa7a6d199d6e8b0ba11
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
---
 src/soc/intel/jasperlake/Kconfig              |  1 +
 src/soc/intel/jasperlake/acpi/southbridge.asl |  3 ---
 src/soc/intel/jasperlake/pmc.c                | 10 ++++++++++
 3 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig
index c40c1534d2..9eb7c83694 100644
--- a/src/soc/intel/jasperlake/Kconfig
+++ b/src/soc/intel/jasperlake/Kconfig
@@ -41,6 +41,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_BLOCK_ACPI
 	select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO
 	select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT
+	select SOC_INTEL_COMMON_BLOCK_ACPI_PEP
 	select SOC_INTEL_COMMON_BLOCK_CAR
 	select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
 	select SOC_INTEL_COMMON_BLOCK_CNVI
diff --git a/src/soc/intel/jasperlake/acpi/southbridge.asl b/src/soc/intel/jasperlake/acpi/southbridge.asl
index e623cc35a9..93e538edc3 100644
--- a/src/soc/intel/jasperlake/acpi/southbridge.asl
+++ b/src/soc/intel/jasperlake/acpi/southbridge.asl
@@ -44,9 +44,6 @@
 /* PCI _OSC */
 #include <soc/intel/common/acpi/pci_osc.asl>
 
-/* Intel Power Engine Plug-in */
-#include <soc/intel/common/block/acpi/acpi/pep.asl>
-
 /* EMMC/SD card */
 #include "scs.asl"
 
diff --git a/src/soc/intel/jasperlake/pmc.c b/src/soc/intel/jasperlake/pmc.c
index dce791c692..6223ed7eee 100644
--- a/src/soc/intel/jasperlake/pmc.c
+++ b/src/soc/intel/jasperlake/pmc.c
@@ -4,6 +4,7 @@
 #include <console/console.h>
 #include <device/mmio.h>
 #include <device/device.h>
+#include <intelblocks/acpi.h>
 #include <intelblocks/pmc.h>
 #include <intelblocks/pmclib.h>
 #include <intelblocks/rtc.h>
@@ -101,9 +102,18 @@ static void pm1_enable_pwrbtn_smi(void *unused)
 
 BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, pm1_enable_pwrbtn_smi, NULL);
 
+static void pmc_fill_ssdt(const struct device *dev)
+{
+	if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_PEP))
+		generate_acpi_power_engine();
+}
+
 struct device_operations pmc_ops = {
 	.read_resources		= soc_pmc_read_resources,
 	.set_resources		= noop_set_resources,
 	.init			= soc_acpi_mode_init,
 	.enable			= pmc_init,
+#if CONFIG(HAVE_ACPI_TABLES)
+	.acpi_fill_ssdt		= pmc_fill_ssdt,
+#endif
 };