From 77c5d898aecbb15b37e4458cd32ca95f10e2264e Mon Sep 17 00:00:00 2001 From: "Chris.Wang" Date: Thu, 16 Mar 2023 15:24:02 +0800 Subject: [PATCH] mb/google/skyrim/var/winterhold: adjust the eDP panel power sequence set pwr_on_varybl_to_blon to 0x1c, which means fw will delay 112ms between backlight on and vary backlight. BUG=b:271704149 BRANCH=none TEST=Build; Verify the UPD was passed to system integrated table; measure the power on sequence on whiterun Signed-off-by: Chris.Wang Change-Id: Ib966d2ebd4ef4a8085695901ec5da160f467e32e Reviewed-on: https://review.coreboot.org/c/coreboot/+/73753 Tested-by: build bot (Jenkins) Reviewed-by: Jason Glenesk Reviewed-by: Felix Held --- .../google/skyrim/variants/winterhold/overridetree.cb | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb index 0cf9ba588b..4297f903b0 100644 --- a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb @@ -112,6 +112,9 @@ chip soc/amd/mendocino register "dxio_tx_vboost_enable" = "1" + # The unit is set to one per 4ms + register "pwr_on_vary_bl_to_blon" = "0x1c" + device ref gpp_bridge_1 on # Required so the NVMe gets placed into D3 when entering S0i3. chip drivers/pcie/rtd3/device