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google/chell: Fix USB port assignment 

The PCH pin names in the schematic were incorrectly labeled.

BUG=chrome-os-partner:46289
BRANCH=none
TEST=build and boot on chell

Change-Id: I6153137b7c04d22db5b3f00f5eaf3f400f4c344c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6f362900b0635dc392c63b25a88a7723f22b467a
Original-Change-Id: If6f8744f020a35a76647366b247723b03c02991a
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/310061
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12324
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Duncan Laurie 2015-10-30 17:55:05 -07:00 committed by Patrick Georgi
parent 47657ea1e1
commit 77d37d21db
1 changed files with 4 additions and 4 deletions
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8
src/mainboard/google/chell/devicetree.cb
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@ -54,11 +54,11 @@ chip soc/intel/skylake
register "PcieRpClkReqNumber[4]" = "2" register "PcieRpClkReqNumber[4]" = "2"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C" # Type-C Port 1 register "usb2_ports[0]" = "USB2_PORT_TYPE_C" # Type-C Port 1
register "usb2_ports[1]" = "USB2_PORT_MID" # Type-A Port register "usb2_ports[2]" = "USB2_PORT_TYPE_C" # Type-C Port 2
register "usb2_ports[2]" = "USB2_PORT_FLEX" # Camera
register "usb2_ports[3]" = "USB2_PORT_MID" # Bluetooth register "usb2_ports[3]" = "USB2_PORT_MID" # Bluetooth
register "usb2_ports[4]" = "USB2_PORT_MID" # SD register "usb2_ports[5]" = "USB2_PORT_MID" # Type-A Port
register "usb2_ports[5]" = "USB2_PORT_TYPE_C" # Type-C Port 2 register "usb2_ports[7]" = "USB2_PORT_FLEX" # Camera
register "usb2_ports[9]" = "USB2_PORT_MID" # SD
register "usb3_ports[0]" = "USB3_PORT_DEFAULT" # Type-C Port 1 register "usb3_ports[0]" = "USB3_PORT_DEFAULT" # Type-C Port 1
register "usb3_ports[1]" = "USB3_PORT_DEFAULT" # Type-C Port 2 register "usb3_ports[1]" = "USB3_PORT_DEFAULT" # Type-C Port 2