AGESA: Fork for new cache-as-ram init code
To gradually consolidate and improve AGESA board romstages, fork the original CAR setup code as a separate file. It becomes too messy with preprocessor to attempt make changes within the same file, and at end of patchset original becomes obsolete. Change-Id: I256b675b1ab9e13c2bcc956e0d67c6c03e91f2ed Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18620 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Kyösti Mälkki
parent
967d94d626
commit
77d3c4b690
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@ -23,7 +23,11 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb
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romstage-y += s3_resume.c
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ramstage-y += s3_mtrr.c
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ifeq ($(CONFIG_AGESA_LEGACY), y)
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cpu_incs-y += $(src)/cpu/amd/agesa/cache_as_ram_legacy.inc
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else
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cpu_incs-y += $(src)/cpu/amd/agesa/cache_as_ram.inc
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endif
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romstage-y += heapmanager.c
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ramstage-y += heapmanager.c
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@ -0,0 +1,170 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/******************************************************************************
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* AMD Generic Encapsulated Software Architecture
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*
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* $Workfile:: cache_as_ram.inc
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*
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* Description: cache_as_ram.inc - AGESA Module Entry Point for GCC complier
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*
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******************************************************************************
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*/
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#include "gcccar.inc"
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#include <cpu/x86/cache.h>
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/*
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* XMM map:
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* xmm0: BIST
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* xmm1: backup ebx -- cpu_init_detected
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*/
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.code32
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.globl cache_as_ram_setup, disable_cache_as_ram, cache_as_ram_setup_out
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cache_as_ram_setup:
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post_code(0xa0)
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/* enable SSE2 128bit instructions */
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/* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */
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movl %cr4, %eax
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orl $(3<<9), %eax
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movl %eax, %cr4
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/* Get the cpu_init_detected */
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mov $1, %eax
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cpuid
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shr $24, %ebx
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/* Save the BIST result */
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cvtsi2sd %ebp, %xmm0
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/* for normal part %ebx already contain cpu_init_detected from fallback call */
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/* Save the cpu_init_detected */
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cvtsi2sd %ebx, %xmm1
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post_code(0xa1)
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AMD_ENABLE_STACK
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/* Align the stack. */
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and $0xFFFFFFF0, %esp
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#ifdef __x86_64__
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/* switch to 64 bit long mode */
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mov %esi, %ecx
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add $0, %ecx # core number
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xor %eax, %eax
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lea (0x1000+0x23)(%ecx), %edi
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mov %edi, (%ecx)
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mov %eax, 4(%ecx)
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lea 0x1000(%ecx), %edi
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movl $0x000000e3, 0x00(%edi)
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movl %eax, 0x04(%edi)
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movl $0x400000e3, 0x08(%edi)
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movl %eax, 0x0c(%edi)
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movl $0x800000e3, 0x10(%edi)
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movl %eax, 0x14(%edi)
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movl $0xc00000e3, 0x18(%edi)
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movl %eax, 0x1c(%edi)
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# load ROM based identity mapped page tables
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mov %ecx, %eax
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mov %eax, %cr3
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# enable PAE
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mov %cr4, %eax
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bts $5, %eax
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mov %eax, %cr4
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# enable long mode
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mov $0xC0000080, %ecx
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rdmsr
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bts $8, %eax
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wrmsr
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# enable paging
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mov %cr0, %eax
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bts $31, %eax
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mov %eax, %cr0
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# use call far to switch to 64-bit code segment
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ljmp $0x18, $1f
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1:
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/* Pass the cpu_init_detected */
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cvtsd2si %xmm1, %esi
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/* Pass the BIST result */
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cvtsd2si %xmm0, %edi
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.code64
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call cache_as_ram_main
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.code32
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#else
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/* Restore the BIST result */
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cvtsd2si %xmm0, %edx
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/* Restore the cpu_init_detected */
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cvtsd2si %xmm1, %ebx
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/* Must maintain 16-byte stack alignment here. */
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pushl $0x0
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pushl $0x0
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pushl %ebx /* init detected */
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pushl %edx /* bist */
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call cache_as_ram_main
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#endif
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/* Should never see this postcode */
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post_code(0xaf)
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stop:
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jmp stop
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disable_cache_as_ram:
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/* Save return stack */
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movd 0(%esp), %xmm1
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movd %esp, %xmm0
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/* Disable cache */
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movl %cr0, %eax
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orl $CR0_CacheDisable, %eax
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movl %eax, %cr0
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AMD_DISABLE_STACK
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/* enable cache */
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movl %cr0, %eax
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andl $0x9fffffff, %eax
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movl %eax, %cr0
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xorl %eax, %eax
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/* Restore the return stack */
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wbinvd
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movd %xmm0, %esp
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movd %xmm1, (%esp)
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ret
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cache_as_ram_setup_out:
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#ifdef __x86_64__
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.code64
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#endif
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