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Move several i945 config #defines from romstage.c to Kconfig. 

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5891 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Patrick Georgi 2010-10-01 08:02:45 +00:00
parent 66d1687b92
commit 77d6683edd
12 changed files with 66 additions and 49 deletions
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2
src/mainboard/getac/p470/Kconfig
View File

@ -43,6 +43,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select CACHE_AS_RAM
select GFXUMA
select TINY_BOOTBLOCK
select I945GM
select CHANNEL_XOR_RANDOMIZATION
config MAINBOARD_DIR
string

4
src/mainboard/getac/p470/romstage.c
View File

@ -19,10 +19,6 @@
* MA 02110-1301 USA
*/
/* Configuration of the i945 driver */
#define CHIPSET_I945GM 1
#define CHANNEL_XOR_RANDOMIZATION 1
#include <stdint.h>
#include <string.h>
#include <arch/io.h>

2
src/mainboard/ibase/mb899/Kconfig
View File

@ -20,6 +20,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select CACHE_AS_RAM
select GFXUMA
select TINY_BOOTBLOCK
select I945GM
select CHANNEL_XOR_RANDOMIZATION
config MAINBOARD_DIR
string

5
src/mainboard/ibase/mb899/romstage.c
View File

@ -19,11 +19,6 @@
// __PRE_RAM__ means: use "unsigned" for device, not a struct.
/* Configuration of the i945 driver */
#define CHIPSET_I945GM 1
//#define OVERRIDE_CLOCK_DISABLE 1
#define CHANNEL_XOR_RANDOMIZATION 1
#include <stdint.h>
#include <string.h>
#include <arch/io.h>

2
src/mainboard/intel/d945gclf/Kconfig
View File

@ -40,6 +40,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select BOARD_ROMSIZE_KB_512
select GFXUMA
select TINY_BOOTBLOCK
select I945GC
select CHANNEL_XOR_RANDOMIZATION
config MAINBOARD_DIR
string

4
src/mainboard/intel/d945gclf/romstage.c
View File

@ -19,10 +19,6 @@
// __PRE_RAM__ means: use "unsigned" for device, not a struct.
/* Configuration of the i945 driver */
#define CHIPSET_I945GC 1
#define CHANNEL_XOR_RANDOMIZATION 1
#include <stdint.h>
#include <string.h>
#include <arch/io.h>

3
src/mainboard/kontron/986lcd-m/Kconfig
View File

@ -20,6 +20,9 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select CACHE_AS_RAM
select GFXUMA
select TINY_BOOTBLOCK
select CHANNEL_XOR_RANDOMIZATION
select I945GM
select OVERRIDE_CLOCK_DISABLE
config MAINBOARD_DIR
string

13
src/mainboard/kontron/986lcd-m/romstage.c
View File

@ -19,19 +19,6 @@
// __PRE_RAM__ means: use "unsigned" for device, not a struct.
/* Configuration of the i945 driver */
#define CHIPSET_I945GM 1
/* Usually system firmware turns off system memory clock signals to
* unused SO-DIMM slots to reduce EMI and power consumption.
* However, the Kontron 986LCD-M does not like unused clock signals to
* be disabled. If other similar mainboard occur, it would make sense
* to make this an entry in the sysinfo structure, and pre-initialize that
* structure in the mainboard's romstage.c main() function. For now a
* #define will do.
*/
#define OVERRIDE_CLOCK_DISABLE 1
#define CHANNEL_XOR_RANDOMIZATION 1
#include <stdint.h>
#include <string.h>
#include <arch/io.h>

6
src/mainboard/roda/rk886ex/Kconfig
View File

@ -19,6 +19,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_ACPI_TABLES
select HAVE_ACPI_RESUME
select BOARD_ROMSIZE_KB_1024
select I945GM
select CHANNEL_XOR_RANDOMIZATION
config MAINBOARD_DIR
string
@ -56,4 +58,8 @@ config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
hex
default 0x6886
config MAXIMUM_SUPPORTED_FREQUENCY
int
default 400
endif # BOARD_RODA_RK886EX

6
src/mainboard/roda/rk886ex/romstage.c
View File

@ -21,12 +21,6 @@
// __PRE_RAM__ means: use "unsigned" for device, not a struct.
/* Configuration of the i945 driver */
#define CHIPSET_I945GM 1
#define CHANNEL_XOR_RANDOMIZATION 1
// Rocky freezing temperature settings:
#define MAXIMUM_SUPPORTED_FREQUENCY 400
#include <stdint.h>
#include <string.h>
#include <arch/io.h>

38
src/northbridge/intel/i945/Kconfig
View File

@ -26,3 +26,41 @@ config FALLBACK_VGA_BIOS_ID
default "8086,27a2"
depends on NORTHBRIDGE_INTEL_I945
choice
default I945GM
depends on NORTHBRIDGE_INTEL_I945
help
Different i945 variants require slightly different setup.
config I945GM
bool "i945GM (Mobile) chipset"
config I945GC
bool "i945GC chipset"
endchoice
config CHANNEL_XOR_RANDOMIZATION
bool
default n
depends on NORTHBRIDGE_INTEL_I945
config OVERRIDE_CLOCK_DISABLE
bool
default n
depends on NORTHBRIDGE_INTEL_I945
help
Usually system firmware turns off system memory clock
signals to unused SO-DIMM slots to reduce EMI and power
consumption.
However, some boards do not like unused clock signals to
be disabled.
config MAXIMUM_SUPPORTED_FREQUENCY
int
default 0
depends on NORTHBRIDGE_INTEL_I945
help
If non-zero, this designates the maximum DDR frequency
the board supports, despite what the chipset should be
capable of.

30
src/northbridge/intel/i945/raminit.c
View File

@ -90,7 +90,7 @@ static void sdram_dump_mchbar_registers(void)
static int memclk(void)
{
int offset = 0;
#ifdef CHIPSET_I945GM
#if CONFIG_I945GM
offset++;
#endif
switch (((MCHBAR32(CLKCFG) >> 4) & 7) - offset) {
@ -102,7 +102,7 @@ static int memclk(void)
return -1;
}
#ifdef CHIPSET_I945GM
#if CONFIG_I945GM
static int fsbclk(void)
{
switch (MCHBAR32(CLKCFG) & 7) {
@ -114,7 +114,7 @@ static int fsbclk(void)
return -1;
}
#endif
#ifdef CHIPSET_I945GC
#if CONFIG_I945GC
static int fsbclk(void)
{
switch (MCHBAR32(CLKCFG) & 7) {
@ -131,8 +131,8 @@ static int sdram_capabilities_max_supported_memory_frequency(void)
{
u32 reg32;
#ifdef MAXIMUM_SUPPORTED_FREQUENCY
return MAXIMUM_SUPPORTED_FREQUENCY;
#if CONFIG_MAXIMUM_SUPPORTED_FREQUENCY
return CONFIG_MAXIMUM_SUPPORTED_FREQUENCY;
#endif
reg32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xe4); /* CAPID0 + 4 */
@ -1045,7 +1045,7 @@ static const u32 *slew_group_lookup(int dual_channel, int index)
return nc;
}
#ifdef CHIPSET_I945GM
#if CONFIG_I945GM
/* Strength multiplier tables */
static const u8 dual_channel_strength_multiplier[] = {
0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
@ -1101,7 +1101,7 @@ static const u8 single_channel_strength_multiplier[] = {
0x33, 0x00, 0x11, 0x00, 0x44, 0x44, 0x33, 0x11
};
#endif
#ifdef CHIPSET_I945GC
#if CONFIG_I945GC
static const u8 dual_channel_strength_multiplier[] = {
0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
@ -2155,7 +2155,7 @@ static void sdram_program_clock_crossing(void)
/**
* We add the indices according to our clocks from CLKCFG.
*/
#ifdef CHIPSET_I945GM
#if CONFIG_I945GM
static const u32 data_clock_crossing[] = {
0x00100401, 0x00000000, /* DDR400 FSB400 */
0xffffffff, 0xffffffff, /* nonexistant */
@ -2201,7 +2201,7 @@ static void sdram_program_clock_crossing(void)
};
#endif
#ifdef CHIPSET_I945GC
#if CONFIG_I945GC
/* i945 G/P */
static const u32 data_clock_crossing[] = {
0xffffffff, 0xffffffff, /* nonexistant */
@ -2420,7 +2420,7 @@ static void sdram_post_jedec_initialization(struct sys_info *sysinfo)
if (sysinfo->interleaved) {
reg32 = MCHBAR32(DCC);
#if CHANNEL_XOR_RANDOMIZATION
#if CONFIG_CHANNEL_XOR_RANDOMIZATION
reg32 &= ~(1 << 10);
reg32 |= (1 << 9);
#else
@ -2792,10 +2792,10 @@ static void sdram_enable_memory_clocks(struct sys_info *sysinfo)
{
u8 clocks[2] = { 0, 0 };
#ifdef CHIPSET_I945GM
#if CONFIG_I945GM
#define CLOCKS_WIDTH 2
#endif
#ifdef CHIPSET_I945GC
#if CONFIG_I945GC
#define CLOCKS_WIDTH 3
#endif
if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED)
@ -2810,15 +2810,11 @@ static void sdram_enable_memory_clocks(struct sys_info *sysinfo)
if (sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)
clocks[1] |= ((1 << CLOCKS_WIDTH)-1) << CLOCKS_WIDTH;
#ifdef OVERRIDE_CLOCK_DISABLE
#if CONFIG_OVERRIDE_CLOCK_DISABLE
/* Usually system firmware turns off system memory clock signals
* to unused SO-DIMM slots to reduce EMI and power consumption.
* However, the Kontron 986LCD-M does not like unused clock
* signals to be disabled.
* If other similar mainboard occur, it would make sense to make
* this an entry in the sysinfo structure, and pre-initialize that
* structure in the mainboard's romstage.c main() function.
* For now an #ifdef will do.
*/
clocks[0] = 0xf; /* force all clock gate pairs to enable */