intel/fsp_baytrail: Fix I2C abort logic
A call to i2c_read() for a non-existent address followed by an i2c_read() to a valid address results in a false abort status for the 2nd call. i2c_read(1, 0x40, 0, buf, sizeof(buf)) => 0x2000000 (I2C_ERR_TIMEOUT) i2c_read(1, 0x74, 0, buf, sizeof(buf)) => 0x4000000 (I2C_ERR_ABORT) Because the abort status register is cleared on read and wait_tx_fifo() reads it twice, the returned status does not contain the abort status. Fixing that changed the 2nd read to reflect the abort status. i2c_read(1, 0x40, 0, buf, sizeof(buf)) => 0x2000000 (I2C_ERR_TIMEOUT) i2c_read(1, 0x74, 0, buf, sizeof(buf)) => 0x4000001 (I2C_ERR_ABORT) Bit 0 indicates that the address was not acknowledged by any slave. That's the abort status from the previous transaction. So I added a read of the abort status before starting a transaction in both i2c_read() and i2c_write(). i2c_read(1, 0x40, 0, buf, sizeof(buf)) => 0x2000000 (I2C_ERR_TIMEOUT) i2c_read(1, 0x74, 0, buf, sizeof(buf)) => 0 (I2C_SUCCESS) Tested on a Bay Trail E3845 SoC. Change-Id: I39e4ff4206587267b6fceef58f4a567bf162fbbe Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: https://review.coreboot.org/14160 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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@ -26,12 +26,13 @@
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static int wait_tx_fifo(char *base_adr)
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{
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int i;
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u32 as;
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if (read32(base_adr + I2C_ABORT_SOURCE) & 0x1ffff) {
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as = read32(base_adr + I2C_ABORT_SOURCE) & 0x1ffff;
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if (as) {
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/* Reading back I2C_CLR_TX_ABRT resets abort lock on TX FIFO */
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i = *((volatile unsigned int *)(base_adr + I2C_CLR_TX_ABRT));
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return I2C_ERR_ABORT |
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(*((unsigned int *)(base_adr + I2C_ABORT_SOURCE)) & 0x1ffff);
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i = read32(base_adr + I2C_CLR_TX_ABRT);
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return I2C_ERR_ABORT | as;
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}
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/* Wait here for a free slot in TX-FIFO */
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@ -51,11 +52,13 @@ static int wait_tx_fifo(char *base_adr)
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static int wait_rx_fifo(char *base_adr)
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{
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int i;
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if (read32(base_adr + I2C_ABORT_SOURCE) & 0x1ffff) {
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u32 as;
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as = read32(base_adr + I2C_ABORT_SOURCE) & 0x1ffff;
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if (as) {
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/* Reading back I2C_CLR_TX_ABRT resets abort lock on TX FIFO */
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i = *((volatile unsigned int *)(base_adr + I2C_CLR_TX_ABRT));
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return I2C_ERR_ABORT |
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(*((unsigned int *)(base_adr + I2C_ABORT_SOURCE)) & 0x1ffff);
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i = read32(base_adr + I2C_CLR_TX_ABRT);
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return I2C_ERR_ABORT | as;
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}
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/* Wait here for a received entry in RX-FIFO */
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@ -177,6 +180,10 @@ int i2c_read(unsigned bus, unsigned chip, unsigned addr,
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stat = wait_for_idle(base_ptr);
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if (stat != I2C_SUCCESS)
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return stat;
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/* clear any abort status from a previous transaction */
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read32(base_ptr + I2C_CLR_TX_ABRT);
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/* Now we can program the desired slave address and start transfer */
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write32(base_ptr + I2C_TARGET_ADR, chip & 0xff);
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/* Send address inside slave to read from */
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@ -232,6 +239,10 @@ int i2c_write(unsigned bus, unsigned chip, unsigned addr,
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if (stat) {
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return stat;
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}
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/* clear any abort status from a previous transaction */
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read32(base_ptr + I2C_CLR_TX_ABRT);
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/* Program slave address to use for this transfer */
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write32(base_ptr + I2C_TARGET_ADR, chip & 0xff);
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