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nb/intel/sandybridge/raminit: Make discover_timC_write non cyclic 

The code can't handle cyclic zero runs. Make sure it will never
wrap around by setting the top-most bit to constant one.

Fixes "Mini channel test failed (2)".

Test system:
 * Gigabyte GA-B75M-D3H
 * Intel Pentium CPU G2130

Change-Id: I55e610d984d564bd4675f9318dead6d6c1e288a3
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13853
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Patrick Rudolph 2016-02-28 16:14:45 +01:00 committed by Martin Roth
parent 58c68d56de
commit 77e45d3ecc
1 changed files with 6 additions and 2 deletions
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8
src/northbridge/intel/sandybridge/raminit.c
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@ -3435,9 +3435,12 @@ static void discover_timC_write(ramctr_timing * ctrl)
u32 raw_statistics[MAX_TIMC + 1]; u32 raw_statistics[MAX_TIMC + 1];
int statistics[MAX_TIMC + 1]; int statistics[MAX_TIMC + 1];
/* Make sure rn.start < rn.end */
statistics[MAX_TIMC] = 1;
fill_pattern5(ctrl, channel, pat); fill_pattern5(ctrl, channel, pat);
write32(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel, 0x1f); write32(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel, 0x1f);
for (timC = 0; timC < MAX_TIMC + 1; timC++) { for (timC = 0; timC < MAX_TIMC; timC++) {
FOR_ALL_LANES FOR_ALL_LANES
ctrl->timings[channel][slotrank].lanes[lane].timC = timC; ctrl->timings[channel][slotrank].lanes[lane].timC = timC;
program_timings(ctrl, channel); program_timings(ctrl, channel);
@ -3449,10 +3452,11 @@ static void discover_timC_write(ramctr_timing * ctrl)
} }
FOR_ALL_LANES { FOR_ALL_LANES {
struct run rn; struct run rn;
for (timC = 0; timC <= MAX_TIMC; timC++) for (timC = 0; timC < MAX_TIMC; timC++)
statistics[timC] = statistics[timC] =
!!(raw_statistics[timC] & !!(raw_statistics[timC] &
(1 << lane)); (1 << lane));
rn = get_longest_zero_run(statistics, rn = get_longest_zero_run(statistics,
MAX_TIMC + 1); MAX_TIMC + 1);
if (rn.all) if (rn.all)