From 77eaecf06b238157decfe19fea02eadfa71a9436 Mon Sep 17 00:00:00 2001 From: Usha P Date: Tue, 4 Feb 2020 11:24:25 +0530 Subject: [PATCH] soc/intel/tigerlake: Update PMC Register Base and platform check for JSP Change: 1. PCR_PSF3_TO_SHDW_PMC_REG_BASE_JSP to 0X0A00 for JSP 2. Platform check in espi.c BUG=None TEST= 1. Test for JSL RVP Boot 2. Verify PMC register values are valid for GEN_PMCON and GBLRST_CAUSE from the coreboot console logs. Change-Id: I6017a9703764b5454e7be479c1e08afe614908f1 Signed-off-by: Usha P Signed-off-by: Meera Ravindranath Reviewed-on: https://review.coreboot.org/c/coreboot/+/38704 Reviewed-by: Rizwan Qureshi Reviewed-by: Aamir Bohra Reviewed-by: Subrata Banik Reviewed-by: Karthik Ramasubramanian Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/bootblock/pch.c | 2 +- src/soc/intel/tigerlake/espi.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c index 1654809a6b..cd264d682c 100644 --- a/src/soc/intel/tigerlake/bootblock/pch.c +++ b/src/soc/intel/tigerlake/bootblock/pch.c @@ -41,7 +41,7 @@ #include #define PCR_PSF3_TO_SHDW_PMC_REG_BASE_TGP 0x1100 -#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_JSP 0x0980 +#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_JSP 0xA00 #define PCR_PSFX_TO_SHDW_BAR0 0 #define PCR_PSFX_TO_SHDW_BAR1 0x4 #define PCR_PSFX_TO_SHDW_BAR2 0x8 diff --git a/src/soc/intel/tigerlake/espi.c b/src/soc/intel/tigerlake/espi.c index d07a582a32..7efd210cad 100644 --- a/src/soc/intel/tigerlake/espi.c +++ b/src/soc/intel/tigerlake/espi.c @@ -83,7 +83,7 @@ uint8_t get_pch_series(void) if (lpc_did_hi_byte == 0xA0) return PCH_TGP; - else if (lpc_did_hi_byte == 0x38) + else if (lpc_did_hi_byte == 0x4d) return PCH_JSP; else return PCH_UNKNOWN_SERIES;