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sb/intel/ibexpeak: Align to coreboot's coding style 

Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.

Change-Id: I30512ef7ff7eb091e1f880c43a0a9ecf8625a710
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46530
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-10-17 18:39:04 +02:00 committed by Patrick Georgi
parent e26e9b556d
commit 77f340a707
7 changed files with 92 additions and 92 deletions
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9
src/southbridge/intel/ibexpeak/early_usb.c
View File

@ -35,21 +35,24 @@ void early_usb_init(const struct southbridge_usb_port *portmap)
RCBA32(0x3598) = 0;
reg32 = 0;
for (i = 0; i < TOTAL_USB_PORTS; i++)
for (i = 0; i < TOTAL_USB_PORTS; i++) {
if (!portmap[i].enabled)
reg32 |= (1 << i);
}
RCBA32(USBPDO) = reg32;
reg32 = 0;
/* The OC pins of the first 8 USB ports are mapped in USBOCM1 */
for (i = 0; i < 8; i++)
for (i = 0; i < 8; i++) {
if (portmap[i].enabled && portmap[i].oc_pin >= 0)
reg32 |= (1 << (i + 8 * portmap[i].oc_pin));
}
RCBA32(USBOCM1) = reg32;
reg32 = 0;
/* The OC pins of the remainder 6 USB ports are mapped in USBOCM2 */
for (i = 8; i < TOTAL_USB_PORTS; i++)
for (i = 8; i < TOTAL_USB_PORTS; i++) {
if (portmap[i].enabled && portmap[i].oc_pin >= 4)
reg32 |= (1 << (i - 8 + 8 * (portmap[i].oc_pin - 4)));
}
RCBA32(USBOCM2) = reg32;
/* Relock registers. */

117
src/southbridge/intel/ibexpeak/lpc.c
View File

@ -89,12 +89,13 @@ static void pch_enable_serial_irqs(struct device *dev)
static void pch_pirq_init(struct device *dev)
{
struct device *irq_dev;
/* Interrupt 11 is not used by legacy devices and so can always be used for
PCI interrupts. Full legacy IRQ routing is complicated and hard to
get right. Fortunately all modern OS use MSI and so it's not that big of
an issue anyway. Still we have to provide a reasonable default. Using
interrupt 11 for it everywhere is a working default. ACPI-aware OS can
move it to any interrupt and others will just leave them at default.
/*
* Interrupt 11 is not used by legacy devices and so can always be used for
* PCI interrupts. Full legacy IRQ routing is complicated and hard to
* get right. Fortunately all modern OS use MSI and so it's not that big of
* an issue anyway. Still we have to provide a reasonable default. Using
* interrupt 11 for it everywhere is a working default. ACPI-aware OS can
* move it to any interrupt and others will just leave them at default.
*/
const u8 pirq_routing = 11;
@ -279,49 +280,46 @@ static void mobile5_pm_init(struct device *dev)
printk(BIOS_DEBUG, "Mobile 5 PM init\n");
pci_write_config8(dev, 0xa9, 0x47);
RCBA32 (0x1d44) = 0x00000000;
(void) RCBA32 (0x1d44);
RCBA32 (0x1d48) = 0x00030000;
(void) RCBA32 (0x1d48);
RCBA32 (0x1e80) = 0x000c0801;
(void) RCBA32 (0x1e80);
RCBA32 (0x1e84) = 0x000200f0;
(void) RCBA32 (0x1e84);
RCBA32(0x1d44) = 0x00000000;
(void)RCBA32(0x1d44);
RCBA32(0x1d48) = 0x00030000;
(void)RCBA32(0x1d48);
RCBA32(0x1e80) = 0x000c0801;
(void)RCBA32(0x1e80);
RCBA32(0x1e84) = 0x000200f0;
(void)RCBA32(0x1e84);
const u32 rcba2010[] =
{
const u32 rcba2010[] = {
/* 2010: */ 0x00188200, 0x14000016, 0xbc4abcb5, 0x00000000,
/* 2020: */ 0xf0c9605b, 0x13683040, 0x04c8f16e, 0x09e90170
};
for (i = 0; i < ARRAY_SIZE(rcba2010); i++)
{
RCBA32 (0x2010 + 4 * i) = rcba2010[i];
RCBA32 (0x2010 + 4 * i);
for (i = 0; i < ARRAY_SIZE(rcba2010); i++) {
RCBA32(0x2010 + 4 * i) = rcba2010[i];
RCBA32(0x2010 + 4 * i);
}
RCBA32 (0x2100) = 0x00000000;
(void) RCBA32 (0x2100);
RCBA32 (0x2104) = 0x00000757;
(void) RCBA32 (0x2104);
RCBA32 (0x2108) = 0x00170001;
(void) RCBA32 (0x2108);
RCBA32(0x2100) = 0x00000000;
(void)RCBA32(0x2100);
RCBA32(0x2104) = 0x00000757;
(void)RCBA32(0x2104);
RCBA32(0x2108) = 0x00170001;
(void)RCBA32(0x2108);
RCBA32 (0x211c) = 0x00000000;
(void) RCBA32 (0x211c);
RCBA32 (0x2120) = 0x00010000;
(void) RCBA32 (0x2120);
RCBA32(0x211c) = 0x00000000;
(void)RCBA32(0x211c);
RCBA32(0x2120) = 0x00010000;
(void)RCBA32(0x2120);
RCBA32 (0x21fc) = 0x00000000;
(void) RCBA32 (0x21fc);
RCBA32 (0x2200) = 0x20000044;
(void) RCBA32 (0x2200);
RCBA32 (0x2204) = 0x00000001;
(void) RCBA32 (0x2204);
RCBA32 (0x2208) = 0x00003457;
(void) RCBA32 (0x2208);
RCBA32(0x21fc) = 0x00000000;
(void)RCBA32(0x21fc);
RCBA32(0x2200) = 0x20000044;
(void)RCBA32(0x2200);
RCBA32(0x2204) = 0x00000001;
(void)RCBA32(0x2204);
RCBA32(0x2208) = 0x00003457;
(void)RCBA32(0x2208);
const u32 rcba2210[] =
{
const u32 rcba2210[] = {
/* 2210 */ 0x00000000, 0x00000001, 0xa0fff210, 0x0000df00,
/* 2220 */ 0x00e30880, 0x00000070, 0x00004000, 0x00000000,
/* 2230 */ 0x00e30880, 0x00000070, 0x00004000, 0x00000000,
@ -331,35 +329,32 @@ static void mobile5_pm_init(struct device *dev)
/* 2270 */ 0x00001c01, 0x16000000, 0x00010107, 0x00160000
};
for (i = 0; i < ARRAY_SIZE(rcba2210); i++)
{
RCBA32 (0x2210 + 4 * i) = rcba2210[i];
RCBA32 (0x2210 + 4 * i);
for (i = 0; i < ARRAY_SIZE(rcba2210); i++) {
RCBA32(0x2210 + 4 * i) = rcba2210[i];
RCBA32(0x2210 + 4 * i);
}
const u32 rcba2300[] =
{
const u32 rcba2300[] = {
/* 2300: */ 0x00000000, 0x40000000, 0x4646827b, 0x6e803131,
/* 2310: */ 0x32c77887, 0x00077733, 0x00007447, 0x00000040,
/* 2320: */ 0xcccc0cfc, 0x0fbb0fff
};
for (i = 0; i < ARRAY_SIZE(rcba2300); i++)
{
RCBA32 (0x2300 + 4 * i) = rcba2300[i];
RCBA32 (0x2300 + 4 * i);
for (i = 0; i < ARRAY_SIZE(rcba2300); i++) {
RCBA32(0x2300 + 4 * i) = rcba2300[i];
RCBA32(0x2300 + 4 * i);
}
RCBA32 (0x37fc) = 0x00000000;
(void) RCBA32 (0x37fc);
RCBA32 (0x3dfc) = 0x00000000;
(void) RCBA32 (0x3dfc);
RCBA32 (0x3e7c) = 0xffffffff;
(void) RCBA32 (0x3e7c);
RCBA32 (0x3efc) = 0x00000000;
(void) RCBA32 (0x3efc);
RCBA32 (0x3f00) = 0x0000010b;
(void) RCBA32 (0x3f00);
RCBA32(0x37fc) = 0x00000000;
(void)RCBA32(0x37fc);
RCBA32(0x3dfc) = 0x00000000;
(void)RCBA32(0x3dfc);
RCBA32(0x3e7c) = 0xffffffff;
(void)RCBA32(0x3e7c);
RCBA32(0x3efc) = 0x00000000;
(void)RCBA32(0x3efc);
RCBA32(0x3f00) = 0x0000010b;
(void)RCBA32(0x3f00);
}
static void enable_hpet(void)
@ -573,7 +568,7 @@ void southbridge_inject_dsdt(const struct device *dev)
/* Add it to SSDT. */
acpigen_write_scope("\\");
acpigen_write_name_dword("NVSA", (uintptr_t) gnvs);
acpigen_write_name_dword("NVSA", (uintptr_t)gnvs);
acpigen_pop_len();
}
}

2
src/southbridge/intel/ibexpeak/madt.c
View File

@ -12,7 +12,7 @@ unsigned long acpi_fill_madt(unsigned long current)
current = acpi_create_madt_lapics(current);
/* IOAPIC */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current,
1, IO_APIC_ADDR, 0);
/* INT_SRC_OVR */

13
src/southbridge/intel/ibexpeak/me.c
View File

@ -119,13 +119,13 @@ static inline void read_me_csr(struct mei_csr *csr)
static inline void write_cb(u32 dword)
{
write32(mei_base_address + (MEI_H_CB_WW/sizeof(u32)), dword);
write32(mei_base_address + (MEI_H_CB_WW / sizeof(u32)), dword);
mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE");
}
static inline u32 read_cb(void)
{
u32 dword = read32(mei_base_address + (MEI_ME_CB_RW/sizeof(u32)));
u32 dword = read32(mei_base_address + (MEI_ME_CB_RW / sizeof(u32)));
mei_dump(NULL, dword, MEI_ME_CB_RW, "READ");
return dword;
}
@ -261,9 +261,8 @@ static int mei_recv_msg(struct mei_header *mei, struct mkhi_header *mkhi,
udelay(ME_DELAY);
}
if (!n) {
printk(BIOS_ERR, "ME: timeout waiting for data: expected "
"%u, available %u\n", expected,
me.buffer_write_ptr - me.buffer_read_ptr);
printk(BIOS_ERR, "ME: timeout waiting for data: expected %u, available %u\n",
expected, me.buffer_write_ptr - me.buffer_read_ptr);
return -1;
}
@ -298,8 +297,8 @@ static int mei_recv_msg(struct mei_header *mei, struct mkhi_header *mkhi,
/* Make sure caller passed a buffer with enough space */
if (ndata != (rsp_bytes >> 2)) {
printk(BIOS_ERR, "ME: not enough room in response buffer: "
"%u != %u\n", ndata, rsp_bytes >> 2);
printk(BIOS_ERR, "ME: not enough room in response buffer: %u != %u\n",
ndata, rsp_bytes >> 2);
return -1;
}

2
src/southbridge/intel/ibexpeak/smbus.c
View File

@ -17,7 +17,7 @@ static void pch_smbus_init(struct device *dev)
/* Enable clock gating */
reg16 = pci_read_config32(dev, 0x80);
reg16 &= ~((1 << 8)|(1 << 10)|(1 << 12)|(1 << 14));
reg16 &= ~((1 << 8) | (1 << 10) | (1 << 12) | (1 << 14));
pci_write_config32(dev, 0x80, reg16);
/* Set Receive Slave Address */

7
src/southbridge/intel/ibexpeak/smihandler.c
View File

@ -102,7 +102,7 @@ void southbridge_smi_monitor(void)
RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR
trap_cycle = RCBA32(0x1e10);
for (i=16; i<20; i++) {
for (i = 16; i < 20; i++) {
if (trap_cycle & (1 << i))
mask |= (0xff << ((i - 16) << 2));
}
@ -131,7 +131,10 @@ void southbridge_smi_monitor(void)
}
printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc);
for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
for (i = 0; i < 4; i++) {
if (IOTRAP(i))
printk(BIOS_DEBUG, " TRAP = %d\n", i);
}
printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf);
printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask);
printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");