cpu/intel/haswell: Use new fixed BAR accessors
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I5fb31f88bbf7c2f1e44924ca2d3169257a9598dd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
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@ -88,7 +88,7 @@ static int pcode_ready(void)
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wait_count = 0;
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do {
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if (!(MCHBAR32(BIOS_MAILBOX_INTERFACE) & MAILBOX_RUN_BUSY))
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if (!(mchbar_read32(BIOS_MAILBOX_INTERFACE) & MAILBOX_RUN_BUSY))
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return 0;
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wait_count += delay_step;
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udelay(delay_step);
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@ -107,23 +107,23 @@ static void calibrate_24mhz_bclk(void)
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}
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/* A non-zero value initiates the PCODE calibration. */
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MCHBAR32(BIOS_MAILBOX_DATA) = ~0;
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MCHBAR32(BIOS_MAILBOX_INTERFACE) =
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MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL;
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mchbar_write32(BIOS_MAILBOX_DATA, ~0);
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mchbar_write32(BIOS_MAILBOX_INTERFACE,
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MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL);
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if (pcode_ready() < 0) {
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printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n");
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return;
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}
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err_code = MCHBAR32(BIOS_MAILBOX_INTERFACE) & 0xff;
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err_code = mchbar_read32(BIOS_MAILBOX_INTERFACE) & 0xff;
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printk(BIOS_DEBUG, "PCODE: 24MHz BCLK calibration response: %d\n",
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err_code);
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/* Read the calibrated value. */
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MCHBAR32(BIOS_MAILBOX_INTERFACE) =
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MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_READ_CALIBRATION;
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mchbar_write32(BIOS_MAILBOX_INTERFACE,
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MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_READ_CALIBRATION);
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if (pcode_ready() < 0) {
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printk(BIOS_ERR, "PCODE: mailbox timeout on read.\n");
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@ -131,7 +131,7 @@ static void calibrate_24mhz_bclk(void)
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}
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printk(BIOS_DEBUG, "PCODE: 24MHz BCLK calibration value: 0x%08x\n",
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MCHBAR32(BIOS_MAILBOX_DATA));
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mchbar_read32(BIOS_MAILBOX_DATA));
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}
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static u32 pcode_mailbox_read(u32 command)
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@ -142,7 +142,7 @@ static u32 pcode_mailbox_read(u32 command)
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}
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/* Send command and start transaction */
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MCHBAR32(BIOS_MAILBOX_INTERFACE) = command | MAILBOX_RUN_BUSY;
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mchbar_write32(BIOS_MAILBOX_INTERFACE, command | MAILBOX_RUN_BUSY);
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if (pcode_ready() < 0) {
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printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n");
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@ -150,7 +150,7 @@ static u32 pcode_mailbox_read(u32 command)
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}
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/* Read mailbox */
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return MCHBAR32(BIOS_MAILBOX_DATA);
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return mchbar_read32(BIOS_MAILBOX_DATA);
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}
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static int pcode_mailbox_write(u32 command, u32 data)
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@ -160,10 +160,10 @@ static int pcode_mailbox_write(u32 command, u32 data)
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return -1;
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}
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MCHBAR32(BIOS_MAILBOX_DATA) = data;
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mchbar_write32(BIOS_MAILBOX_DATA, data);
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/* Send command and start transaction */
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MCHBAR32(BIOS_MAILBOX_INTERFACE) = command | MAILBOX_RUN_BUSY;
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mchbar_write32(BIOS_MAILBOX_INTERFACE, command | MAILBOX_RUN_BUSY);
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if (pcode_ready() < 0) {
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printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n");
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@ -365,12 +365,12 @@ void set_power_limits(u8 power_limit_1_time)
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wrmsr(MSR_PKG_POWER_LIMIT, limit);
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/* Set power limit values in MCHBAR as well */
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MCHBAR32(MCH_PKG_POWER_LIMIT_LO) = limit.lo;
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MCHBAR32(MCH_PKG_POWER_LIMIT_HI) = limit.hi;
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mchbar_write32(MCH_PKG_POWER_LIMIT_LO, limit.lo);
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mchbar_write32(MCH_PKG_POWER_LIMIT_HI, limit.hi);
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/* Set DDR RAPL power limit by copying from MMIO to MSR */
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msr.lo = MCHBAR32(MCH_DDR_POWER_LIMIT_LO);
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msr.hi = MCHBAR32(MCH_DDR_POWER_LIMIT_HI);
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msr.lo = mchbar_read32(MCH_DDR_POWER_LIMIT_LO);
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msr.hi = mchbar_read32(MCH_DDR_POWER_LIMIT_HI);
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wrmsr(MSR_DDR_RAPL_LIMIT, msr);
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/* Use nominal TDP values for CPUs with configurable TDP */
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