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cpu/intel/haswell: Use new fixed BAR accessors 

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: I5fb31f88bbf7c2f1e44924ca2d3169257a9598dd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Angel Pons 2021-03-27 20:05:22 +01:00 committed by Nico Huber
parent 528b471f94
commit 7811a45553
1 changed files with 16 additions and 16 deletions
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32
src/cpu/intel/haswell/haswell_init.c
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@ -88,7 +88,7 @@ static int pcode_ready(void)
wait_count = 0; wait_count = 0;
do { do {
if (!(MCHBAR32(BIOS_MAILBOX_INTERFACE) & MAILBOX_RUN_BUSY)) if (!(mchbar_read32(BIOS_MAILBOX_INTERFACE) & MAILBOX_RUN_BUSY))
return 0; return 0;
wait_count += delay_step; wait_count += delay_step;
udelay(delay_step); udelay(delay_step);
@ -107,23 +107,23 @@ static void calibrate_24mhz_bclk(void)
} }
/* A non-zero value initiates the PCODE calibration. */ /* A non-zero value initiates the PCODE calibration. */
MCHBAR32(BIOS_MAILBOX_DATA) = ~0; mchbar_write32(BIOS_MAILBOX_DATA, ~0);
MCHBAR32(BIOS_MAILBOX_INTERFACE) = mchbar_write32(BIOS_MAILBOX_INTERFACE,
MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL; MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL);
if (pcode_ready() < 0) { if (pcode_ready() < 0) {
printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n"); printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n");
return; return;
} }
err_code = MCHBAR32(BIOS_MAILBOX_INTERFACE) & 0xff; err_code = mchbar_read32(BIOS_MAILBOX_INTERFACE) & 0xff;
printk(BIOS_DEBUG, "PCODE: 24MHz BCLK calibration response: %d\n", printk(BIOS_DEBUG, "PCODE: 24MHz BCLK calibration response: %d\n",
err_code); err_code);
/* Read the calibrated value. */ /* Read the calibrated value. */
MCHBAR32(BIOS_MAILBOX_INTERFACE) = mchbar_write32(BIOS_MAILBOX_INTERFACE,
MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_READ_CALIBRATION; MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_READ_CALIBRATION);
if (pcode_ready() < 0) { if (pcode_ready() < 0) {
printk(BIOS_ERR, "PCODE: mailbox timeout on read.\n"); printk(BIOS_ERR, "PCODE: mailbox timeout on read.\n");
@ -131,7 +131,7 @@ static void calibrate_24mhz_bclk(void)
} }
printk(BIOS_DEBUG, "PCODE: 24MHz BCLK calibration value: 0x%08x\n", printk(BIOS_DEBUG, "PCODE: 24MHz BCLK calibration value: 0x%08x\n",
MCHBAR32(BIOS_MAILBOX_DATA)); mchbar_read32(BIOS_MAILBOX_DATA));
} }
static u32 pcode_mailbox_read(u32 command) static u32 pcode_mailbox_read(u32 command)
@ -142,7 +142,7 @@ static u32 pcode_mailbox_read(u32 command)
} }
/* Send command and start transaction */ /* Send command and start transaction */
MCHBAR32(BIOS_MAILBOX_INTERFACE) = command | MAILBOX_RUN_BUSY; mchbar_write32(BIOS_MAILBOX_INTERFACE, command | MAILBOX_RUN_BUSY);
if (pcode_ready() < 0) { if (pcode_ready() < 0) {
printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n"); printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n");
@ -150,7 +150,7 @@ static u32 pcode_mailbox_read(u32 command)
} }
/* Read mailbox */ /* Read mailbox */
return MCHBAR32(BIOS_MAILBOX_DATA); return mchbar_read32(BIOS_MAILBOX_DATA);
} }
static int pcode_mailbox_write(u32 command, u32 data) static int pcode_mailbox_write(u32 command, u32 data)
@ -160,10 +160,10 @@ static int pcode_mailbox_write(u32 command, u32 data)
return -1; return -1;
} }
MCHBAR32(BIOS_MAILBOX_DATA) = data; mchbar_write32(BIOS_MAILBOX_DATA, data);
/* Send command and start transaction */ /* Send command and start transaction */
MCHBAR32(BIOS_MAILBOX_INTERFACE) = command | MAILBOX_RUN_BUSY; mchbar_write32(BIOS_MAILBOX_INTERFACE, command | MAILBOX_RUN_BUSY);
if (pcode_ready() < 0) { if (pcode_ready() < 0) {
printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n"); printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n");
@ -365,12 +365,12 @@ void set_power_limits(u8 power_limit_1_time)
wrmsr(MSR_PKG_POWER_LIMIT, limit); wrmsr(MSR_PKG_POWER_LIMIT, limit);
/* Set power limit values in MCHBAR as well */ /* Set power limit values in MCHBAR as well */
MCHBAR32(MCH_PKG_POWER_LIMIT_LO) = limit.lo; mchbar_write32(MCH_PKG_POWER_LIMIT_LO, limit.lo);
MCHBAR32(MCH_PKG_POWER_LIMIT_HI) = limit.hi; mchbar_write32(MCH_PKG_POWER_LIMIT_HI, limit.hi);
/* Set DDR RAPL power limit by copying from MMIO to MSR */ /* Set DDR RAPL power limit by copying from MMIO to MSR */
msr.lo = MCHBAR32(MCH_DDR_POWER_LIMIT_LO); msr.lo = mchbar_read32(MCH_DDR_POWER_LIMIT_LO);
msr.hi = MCHBAR32(MCH_DDR_POWER_LIMIT_HI); msr.hi = mchbar_read32(MCH_DDR_POWER_LIMIT_HI);
wrmsr(MSR_DDR_RAPL_LIMIT, msr); wrmsr(MSR_DDR_RAPL_LIMIT, msr);
/* Use nominal TDP values for CPUs with configurable TDP */ /* Use nominal TDP values for CPUs with configurable TDP */