soc/qualcomm/sc7280: Enable PCIe driver
Enable PCIe functionality on sc7280 and supply all the needed data for PCIe generic platform driver. BUG=b:182963902,b:216686574,b:181098581 TEST=Verified on Qualcomm sc7280 development board with NVMe card (Koixa NVMe, Model-KBG40ZPZ256G with FW AEGA0102). Confirmed NVMe is getting detected in response to 'storage init' command in depthcharge CLI prompt. Output logs: ->dpch: storage init Initializing NVMe controller 1e0f:0001 Identified NVMe model KBG40ZPZ256G TOSHIBA MEMORY Added NVMe drive "NVMe Namespace 1" lbasize:512, count:0x1dcf32b0 * 0: NVMe Namespace 1 1 devices total Also verified NVMe boot path, that is depthcharge is able to load the kernel image from NVMe storage. Change-Id: I1f79a0ae2dea594d6026d55a15978eeb92a8ff18 Signed-off-by: Prasad Malisetty <quic_pmaliset@quicinc.com> Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66148 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Prasad Malisetty
Shelley Chen
parent
a47a490635
commit
78298f5c8f
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@ -16,6 +16,8 @@ config SOC_QUALCOMM_SC7280
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select HAS_RECOVERY_MRC_CACHE
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select COMPRESS_BOOTBLOCK
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select HAVE_UART_SPECIAL
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select PCI
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select NO_ECAM_MMCONF_SUPPORT
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if SOC_QUALCOMM_SC7280
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@ -46,6 +46,8 @@ ramstage-y += ../common/usb/snps_usb_phy.c
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ramstage-y += ../common/usb/qmpv4_usb_phy.c
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ramstage-y += ../common/aop_load_reset.c
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ramstage-y += cpucp_load_reset.c
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ramstage-$(CONFIG_PCI) += ../common/pcie_common.c
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ramstage-$(CONFIG_PCI) += pcie.c
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################################################################################
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@ -68,4 +68,27 @@
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#define QMP_PHY_PCS_REG_BASE 0x088e9c00
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#define USB_HOST_DWC3_BASE 0x0a60c100
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/* PCIE_1 */
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#define PCIE1_PCIE_PARF 0x01C08000
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#define PCIE1_GEN3X2_PCIE_DBI 0x40000000
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#define PCIE1_GEN3X2_PCIE_ELBI 0x40000F20
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#define PCIE1_GEN3X2_DWC_PCIE_DM_IATU 0x40001000
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#define PCIE1_SPACE_END_ADDR 0x60000000
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#define PCIE1_BCR 0x18D000
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/* QMP PCIE_1 PHY */
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#define PCIE_1_QMP_PHY 0x01C0E000
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/* QMP PHY, Serdes,Tx, Rx and PCS register definitions */
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#define PCIE1_QMP_PHY_PCS_COM 0x01C0EA00
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#define PCE1_QPHY_SERDES 0x01C0E000
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#define PCE1_QPHY_TX0 0x01C0E200
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#define PCE1_QPHY_RX0 0x01C0E400
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#define PCE1_QPHY_TX1 0x01C0E600
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#define PCE1_QPHY_RX1 0x01C0E800
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#define PCE1_QPHY_PCS_MISC 0x01C0EE00
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/* PHY BCR */
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#define GCC_PCIE_1_PHY_BCR 0x18E01C
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#endif /* __SOC_QUALCOMM_SC7280_ADDRESS_MAP_H__ */
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@ -0,0 +1,247 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <device/device.h>
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#include <device/mmio.h>
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#include <device/pci.h>
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#include <device/pci_def.h>
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#include <gpio.h>
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#include <soc/addressmap.h>
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#include <soc/clock.h>
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#include <soc/gpio.h>
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#include <soc/qcom_qmp_phy.h>
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#include <soc/pcie.h>
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#if CONFIG(BOARD_GOOGLE_SENOR)
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#define NVME_REG_EN GPIO(19)
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#else
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/* For Herobrine board and all variants */
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#define NVME_REG_EN GPIO(51)
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#endif
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static const struct qcom_qmp_phy_init_tbl sc7280_qmp_pcie_serdes_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
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};
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static const struct qcom_qmp_phy_init_tbl sc7280_qmp_pcie_tx_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
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QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
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QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
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};
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static const struct qcom_qmp_phy_init_tbl sc7280_qmp_pcie_rx_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
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};
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static const struct qcom_qmp_phy_init_tbl sc7280_qmp_pcie_pcs_tbl[] = {
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
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};
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static const struct qcom_qmp_phy_init_tbl sc7280_qmp_pcie_pcs_misc_tbl[] = {
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
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};
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static const struct qcom_qmp_phy_init_tbl sc7280_qmp_gen3x2_pcie_tx_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
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};
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static const struct qcom_qmp_phy_init_tbl sc7280_qmp_gen3x2_pcie_rx_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
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};
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static const struct qcom_qmp_phy_init_tbl sc7280_qmp_gen3x2_pcie_pcs_tbl[] = {
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
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};
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static const struct qcom_qmp_phy_init_tbl sc7280_qmp_gen3x2_pcie_misc_tbl[] = {
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
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};
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static pcie_cntlr_cfg_t pcie_host = {
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.parf = (void *) PCIE1_PCIE_PARF,
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.dbi_base = (void *) PCIE1_GEN3X2_PCIE_DBI,
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.elbi = (void *) PCIE1_GEN3X2_PCIE_ELBI,
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.atu_base = (void *) PCIE1_GEN3X2_DWC_PCIE_DM_IATU,
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.cfg_base = (void *) PCIE1_GEN3X2_PCIE_DBI + PCIE_EP_CONF_OFFSET,
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.pcie_bcr = (void *) PCIE1_BCR,
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.qmp_phy_bcr = (void *) GCC_PCIE_1_PHY_BCR,
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.lanes = PCIE_3x2_NUM_LANES,
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.cfg_size = PCIE_EP_CONF_SIZE,
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.perst = GPIO(2),
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/* Store the IO and MEM space settings for future use by the ATU */
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.io.phys_start = PCIE1_GEN3X2_PCIE_DBI + PCIE_IO_SPACE_OFFSET,
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.io.size = PCIE_IO_SPACE_SIZE,
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.mem.phys_start = PCIE1_GEN3X2_PCIE_DBI + PCIE_MMIO_SPACE_OFFSET,
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.mem.size = PCIE1_SPACE_END_ADDR,
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};
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static pcie_qmp_phy_cfg_t pcie1_qmp_phy_3x2 = {
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.qmp_phy_base = (void *) PCIE_1_QMP_PHY,
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.serdes = (void *) PCE1_QPHY_SERDES,
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.tx0 = (void *) PCE1_QPHY_TX0,
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.rx0 = (void *) PCE1_QPHY_RX0,
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.pcs = (void *) PCIE1_QMP_PHY_PCS_COM,
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.tx1 = (void *) PCE1_QPHY_TX1,
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.rx1 = (void *) PCE1_QPHY_RX1,
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.pcs_misc = (void *) PCE1_QPHY_PCS_MISC,
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.serdes_tbl = sc7280_qmp_pcie_serdes_tbl,
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.serdes_tbl_num = ARRAY_SIZE(sc7280_qmp_pcie_serdes_tbl),
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.tx_tbl = sc7280_qmp_pcie_tx_tbl,
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.tx_tbl_num = ARRAY_SIZE(sc7280_qmp_pcie_tx_tbl),
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.tx_tbl_sec = sc7280_qmp_gen3x2_pcie_tx_tbl,
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.tx_tbl_num_sec = ARRAY_SIZE(sc7280_qmp_gen3x2_pcie_tx_tbl),
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.rx_tbl = sc7280_qmp_pcie_rx_tbl,
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.rx_tbl_num = ARRAY_SIZE(sc7280_qmp_pcie_rx_tbl),
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.rx_tbl_sec = sc7280_qmp_gen3x2_pcie_rx_tbl,
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.rx_tbl_num_sec = ARRAY_SIZE(sc7280_qmp_gen3x2_pcie_rx_tbl),
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.pcs_tbl = sc7280_qmp_pcie_pcs_tbl,
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.pcs_tbl_num = ARRAY_SIZE(sc7280_qmp_pcie_pcs_tbl),
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.pcs_tbl_sec = sc7280_qmp_gen3x2_pcie_pcs_tbl,
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.pcs_tbl_num_sec = ARRAY_SIZE(sc7280_qmp_gen3x2_pcie_pcs_tbl),
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.pcs_misc_tbl = sc7280_qmp_pcie_pcs_misc_tbl,
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.pcs_misc_tbl_num = ARRAY_SIZE(sc7280_qmp_pcie_pcs_misc_tbl),
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.pcs_misc_tbl_sec = sc7280_qmp_gen3x2_pcie_misc_tbl,
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.pcs_misc_tbl_num_sec = ARRAY_SIZE(sc7280_qmp_gen3x2_pcie_misc_tbl),
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};
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/* Enable PIPE clock */
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int qcom_dw_pcie_enable_pipe_clock(void)
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{
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int ret;
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/* Set pipe clock source */
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ret = clock_configure_mux(GCC_PCIE_1_PIPE_MUXR, PCIE_1_PIPE_SRC_SEL);
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if (ret) {
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printk(BIOS_ERR, " %s(): Pipe clock enable failed\n", __func__);
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return -1;
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}
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/* Enable pipe clock */
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ret = clock_enable_pcie(PCIE_1_PIPE_CLK);
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if (ret) {
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printk(BIOS_ERR, "Failed to enable pipe clock\n");
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return -1;
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}
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return ret;
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}
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/* Enable controller specific clocks */
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int32_t qcom_dw_pcie_enable_clock(void)
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{
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int32_t ret, clk;
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/* Enable gdsc before enable pcie clocks */
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ret = clock_enable_gdsc(PCIE_1_GDSC);
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if (ret) {
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printk(BIOS_ERR, "Failed to enable gdsc\n");
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return ret;
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}
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||||
/* Enable pcie and PHY clocks */
|
||||
for (clk = PCIE_1_SLV_Q2A_AXI_CLK; clk < PCIE_CLK_COUNT - 3; clk++) {
|
||||
ret = clock_enable_pcie(clk);
|
||||
if (ret) {
|
||||
printk(BIOS_ERR, "Failed to enable %d clock\n", clk);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Turn on NVMe */
|
||||
void gcom_pcie_power_on_ep(void)
|
||||
{
|
||||
gpio_output(NVME_REG_EN, 1);
|
||||
}
|
||||
|
||||
void gcom_pcie_get_config(struct qcom_pcie_cntlr_t *host_cfg)
|
||||
{
|
||||
host_cfg->cntlr_cfg = &pcie_host;
|
||||
host_cfg->qmp_phy_cfg = &pcie1_qmp_phy_3x2;
|
||||
}
|
||||
|
|
@ -6,6 +6,14 @@
|
|||
#include <soc/symbols_common.h>
|
||||
#include <soc/aop_common.h>
|
||||
#include <soc/cpucp.h>
|
||||
#include <soc/pcie.h>
|
||||
|
||||
static struct device_operations pci_domain_ops = {
|
||||
.read_resources = &qcom_pci_domain_read_resources,
|
||||
.set_resources = &pci_domain_set_resources,
|
||||
.scan_bus = &pci_domain_scan_bus,
|
||||
.enable = &qcom_setup_pcie_host,
|
||||
};
|
||||
|
||||
static void soc_read_resources(struct device *dev)
|
||||
{
|
||||
|
|
@ -36,7 +44,11 @@ static struct device_operations soc_ops = {
|
|||
|
||||
static void enable_soc_dev(struct device *dev)
|
||||
{
|
||||
dev->ops = &soc_ops;
|
||||
/* Set the operations if it is a special bus type */
|
||||
if (dev->path.type == DEVICE_PATH_DOMAIN)
|
||||
dev->ops = &pci_domain_ops;
|
||||
else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
|
||||
dev->ops = &soc_ops;
|
||||
}
|
||||
|
||||
struct chip_operations soc_qualcomm_sc7280_ops = {
|
||||
|
|
|
|||
Loading…
Reference in New Issue