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drop support for various (old) PPC CPUs as per discussion from 9/10/9 

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4845 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2009-10-24 18:46:08 +00:00 committed by Stefan Reinauer
parent 95fca9e8f4
commit 7833048e1f
23 changed files with 0 additions and 1683 deletions
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1
src/cpu/ppc/Kconfig
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#

6
src/cpu/ppc/Makefile.inc
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#subdirs-y += ../simple_init
#subdirs-y += mpc74xx
#subdirs-y += ppc4xx
#subdirs-y += ppc7xx
#subdirs-y += ppc970

23
src/cpu/ppc/mpc74xx/Config.lb
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##
## CPU initialization
##
uses CONFIG_RAMBASE
uses CONFIG_USE_DCACHE_RAM
uses CONFIG_DCACHE_RAM_BASE
uses CONFIG_DCACHE_RAM_SIZE
##
## Use cache ram for initial setup
##
default CONFIG_USE_DCACHE_RAM=1
## Set dcache ram above coreboot image
default CONFIG_DCACHE_RAM_BASE=CONFIG_RAMBASE+0x100000
## Dcache size is 32Kb
default CONFIG_DCACHE_RAM_SIZE=0x8000
initinclude "FAMILY_INIT" cpu/ppc/mpc74xx/mpc74xx.inc
object cache.S
initobject cache.S
dir /cpu/simple_init

23
src/cpu/ppc/mpc74xx/cache.S
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#define ASM
#include "ppcreg.h"
#include <ppc_asm.tmpl>
#define NUM_CACHE_LINES 128*8
#define L1_CACHE_LINE_SIZE 32
#define cache_flush_buffer 0x1000
/*
* Flush data cache
* Do this by just reading lots of stuff into the cache.
*/
.globl flush_dcache
flush_dcache:
lis r3,cache_flush_buffer@h
ori r3,r3,cache_flush_buffer@l
li r4,NUM_CACHE_LINES
mtctr r4
0: lwz r4,0(r3)
addi r3,r3,L1_CACHE_LINE_SIZE
bdnz 0b
blr

192
src/cpu/ppc/mpc74xx/mpc74xx.inc
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2000 AG Electronics Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/*
* The aim of this code is to bring the machine from power-on to the point
* where we can jump to the the main coreboot entry point hardwaremain()
* which is written in C.
*
* At power-on, we have no RAM, a memory-mapped I/O space, and we are executing
* out of ROM, generally at 0xfff00100.
*
* Before we jump to harwaremain() we want to do the following:
*
* - enable L1 I/D caches, otherwise performance will be slow
* - set up DBATs for the following regions:
* - RAM (generally 0x00000000 -> 0x7fffffff)
* - ROM (CONFIG_ROMBASE -> CONFIG_ROMBASE + CONFIG_ROM_SIZE)
* - I/O (generally 0xfc000000 -> 0xfdffffff)
* - the main purpose for setting up the DBATs is so the I/O region
* can be marked cache inhibited/write through
* - set up IBATs for RAM and ROM
*
*/
#include <ppc74xx.h>
#define BSP_IOREGION1 0x80000000
#define BSP_IOMASK1 BAT_BL_256M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
#define BSP_IOREGION2 0xFD000000
#define BSP_IOMASK2 BAT_BL_64M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
isync
sync
/*
* Disable dcache and MMU
* Clear IR & DR
* Enable FP
*/
li r0, 0
mtspr HID0, r0
sync
mfmsr r3
li r4, 0x0030 /* IR & DR */
andc r3, r3, r4
ori r3, r3, 0x2000 /* FP */
mtmsr r3
isync
sync
/*
* Invalidate D & I BATS
*/
mtibatu 0, r0
mtibatu 1, r0
mtibatu 2, r0
mtibatu 3, r0
isync
mtdbatu 0, r0
mtdbatu 1, r0
mtdbatu 2, r0
mtdbatu 3, r0
isync
/*
* Clear segment registers (coreboot doesn't use these)
*/
mtsr 0, r0
isync
mtsr 1, r0
isync
mtsr 2, r0
isync
mtsr 3, r0
isync
mtsr 4, r0
isync
mtsr 5, r0
isync
mtsr 6, r0
isync
mtsr 7, r0
isync
mtsr 8, r0
isync
mtsr 9, r0
isync
mtsr 10, r0
isync
mtsr 11, r0
isync
mtsr 12, r0
isync
mtsr 13, r0
isync
mtsr 14, r0
isync
mtsr 15, r0
isync
/*
* Set up DBATs
*
* DBAT0 covers RAM (0 -> 0x0FFFFFFF) (256Mb)
* DBAT1 covers PCI memory and ROM (0xFD000000 -> 0xFFFFFFFF) (64Mb)
* DBAT2 covers PCI memory (0x80000000 -> 0x8FFFFFFF) (256Mb)
* DBAT3 is not used
*/
lis r2, 0@h
ori r3, r2, BAT_BL_256M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
ori r2, r2, BAT_READ_WRITE | BAT_GUARDED
mtdbatu 0, r3
mtdbatl 0, r2
isync
lis r2, BSP_IOREGION2@h
ori r3, r2, BAT_BL_64M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
ori r2, r2, BAT_CACHE_INHIBITED | BAT_GUARDED | BAT_READ_WRITE
mtdbatu 1, r3
mtdbatl 1, r2
isync
lis r2, BSP_IOREGION1@h
ori r3, r2, BAT_BL_256M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
ori r2, r2, BAT_CACHE_INHIBITED | BAT_GUARDED | BAT_READ_WRITE
mtdbatu 2, r3
mtdbatl 2, r2
isync
/*
* IBATS
*
* IBAT0 covers RAM (0 -> 256Mb)
* IBAT1 covers ROM (CONFIG_ROMBASE -> CONFIG_ROMBASE+CONFIG_ROM_SIZE)
*/
lis r2, 0@h
ori r3, r2, BAT_BL_256M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
ori r2, r2, BAT_READ_WRITE
mtibatu 0, r3
mtibatl 0, r2
isync
lis r2, CONFIG_ROMBASE@h
#if CONFIG_ROM_SIZE > 1048576
ori r3, r2, BAT_BL_16M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
#else
ori r3, r2, BAT_BL_1M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
#endif
ori r2, r2, BAT_READ_ONLY
mtibatu 1, r3
mtibatl 1, r2
isync
/*
* Enable MMU
*/
mfmsr r2
ori r2, r2, MSR_DR | MSR_IR
mtmsr r2
isync
sync
/*
* Enable and invalidate the L1 icache
*/
mfspr r2, HID0
ori r2, r2, HID0_ICE | HID0_ICFI
isync
mtspr HID0, r2
/*
* Enable and invalidate the L1 dcache
*/
mfspr r2, HID0
ori r2, r2, HID0_DCE | HID0_DCFI
sync
mtspr HID0, r2

29
src/cpu/ppc/ppc4xx/Config.lb
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##
## CPU initialization
##
uses CONFIG_RAMBASE
uses CONFIG_USE_DCACHE_RAM
uses CONFIG_DCACHE_RAM_BASE
uses CONFIG_DCACHE_RAM_SIZE
##
## PPC4XX always uses cache ram for initial setup
##
default CONFIG_USE_DCACHE_RAM=1
## Set dcache ram above coreboot image
default CONFIG_DCACHE_RAM_BASE=CONFIG_RAMBASE+0x100000
## Dcache size is 16Kb
default CONFIG_DCACHE_RAM_SIZE=16384
initinclude "FAMILY_INIT" cpu/ppc/ppc4xx/ppc4xx.inc
initobject cache.S
initobject sdram.c
initobject clock.c
config chip.h
object clock.o
object cache.S
object pci_domain.o
driver pci_bridge.o
dir /cpu/simple_init

179
src/cpu/ppc/ppc4xx/cache.S
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/*
* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
* Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*
* This source code has been made available to you by IBM on an AS-IS
* basis. Anyone receiving this source is licensed under IBM
* copyrights to use it in any way he or she deems fit, including
* copying it, modifying it, compiling it, and redistributing it either
* with or without modifications. No license under IBM patents or
* patent applications is to be implied by the copyright license.
*
* Any user of this software should understand that IBM cannot provide
* technical support for this software and will not be responsible for
* any consequences resulting from the use of this software.
*
* Any person who transfers this source code or any derivative work
* must include the IBM copyright notice, this paragraph, and the
* preceding two paragraphs in the transferred software.
*
* COPYRIGHT I B M CORPORATION 1995
* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
*
*/
#include <ppc_asm.tmpl>
#define CACHELINE_SIZE 32 /* 32 bytes (8 words) */
/*
* Cache functions.
*/
.globl invalidate_icache
invalidate_icache:
iccci r0,r0 /* for 405, iccci invalidates the */
blr /* entire I cache */
.globl invalidate_dcache
invalidate_dcache:
li r6,0x0000 /* clear GPR 6 */
/* Do loop for # of dcache congruence classes. */
li r7,(CONFIG_DCACHE_RAM_SIZE / CACHELINE_SIZE / 2)
/* NOTE: dccci invalidates both */
mtctr r7 /* ways in the D cache */
1:
dccci 0,r6 /* invalidate line */
addi r6,r6, CACHELINE_SIZE /* bump to next line */
bdnz 1b
blr
.globl flush_dcache
flush_dcache:
lis r9,0x0002 /* set mask for EE and CE msr bits */
ori r9,r9,0x8000
mfmsr r12 /* save msr */
andc r9,r12,r9
mtmsr r9 /* disable EE and CE */
li r10,0x0001 /* enable data cache for unused memory */
mfdccr r9 /* region 0xF8000000-0xFFFFFFFF via */
or r10,r10,r9 /* bit 31 in dccr */
mtdccr r10
/* do loop for # of congruence classes. */
li r10,(CONFIG_DCACHE_RAM_SIZE / CACHELINE_SIZE / 2)
li r11,(CONFIG_DCACHE_RAM_SIZE / 2) /* D cache set size - 2 way sets */
mtctr r10
li r10,(0xE000-0x10000) /* start at 0xFFFFE000 */
add r11,r10,r11 /* add to get to other side of cache line */
1:
lwz r3,0(r10) /* least recently used side */
lwz r3,0(r11) /* the other side */
dccci r0,r11 /* invalidate both sides */
addi r10,r10,CACHELINE_SIZE /* bump to next line */
addi r11,r11,CACHELINE_SIZE /* bump to next line */
bdnz 1b
sync /* allow memory access to complete */
mtdccr r9 /* restore dccr */
mtmsr r12 /* restore msr */
blr
.globl icache_enable
icache_enable:
mflr r8
bl invalidate_icache
mtlr r8
isync
lis r3,0x8000 /* set bit 0 */
mticcr r3
blr
.globl icache_disable
icache_disable:
lis r3,0x0000 /* clear bit 0 */
mticcr r3
isync
blr
.globl icache_status
icache_status:
mficcr r3
srwi r3, r3, 31 /* >>31 => select bit 0 */
blr
.globl dcache_enable
dcache_enable:
mflr r8
bl invalidate_dcache
mtlr r8
isync
lis r3,0x8000 /* set bit 0 */
mtdccr r3
blr
.globl dcache_disable
dcache_disable:
mflr r8
bl flush_dcache
mtlr r8
lis r3,0x0000 /* clear bit 0 */
mtdccr r3
blr
.globl dcache_status
dcache_status:
mfdccr r3
srwi r3, r3, 31 /* >>31 => select bit 0 */
blr
/*------------------------------------------------------------------------------- */
/* Function: ppcDcbf */
/* Description: Data Cache block flush */
/* Input: r3 = effective address */
/* Output: none. */
/*------------------------------------------------------------------------------- */
.globl ppcDcbf
ppcDcbf:
dcbf r0,r3
blr
/*------------------------------------------------------------------------------- */
/* Function: ppcDcbi */
/* Description: Data Cache block Invalidate */
/* Input: r3 = effective address */
/* Output: none. */
/*------------------------------------------------------------------------------- */
.globl ppcDcbi
ppcDcbi:
dcbi r0,r3
blr
/*------------------------------------------------------------------------------- */
/* Function: ppcSync */
/* Description: Processor Synchronize */
/* Input: none. */
/* Output: none. */
/*------------------------------------------------------------------------------- */
.globl ppcSync
ppcSync:
sync
blr

4
src/cpu/ppc/ppc4xx/chip.h
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struct cpu_ppc_ppc4xx_config
{
};
extern struct chip_operations cpu_ppc_ppc4xx_ops;

181
src/cpu/ppc/ppc4xx/clock.c
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@ -1,181 +0,0 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#include <ppc_asm.tmpl>
#include <ppc.h>
#include <ppc4xx.h>
#include <ppcreg.h>
#include <string.h>
/* ------------------------------------------------------------------------- */
#define ONE_BILLION 1000000000
void get_sys_info (struct ppc4xx_sys_info * sysInfo)
{
unsigned long pllmr;
unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ * 1000);
unsigned pvr = ppc_getpvr();
unsigned long psr;
unsigned long m;
memset(sysInfo, 0, sizeof(*sysInfo));
/*
* Read PLL Mode register
*/
pllmr = mfdcr(CPC0_PLLMR);
/*
* Read Pin Strapping register
*/
psr = mfdcr(CPC0_PSR);
/*
* Determine FWD_DIV.
*/
sysInfo->pllFwdDiv = 8 - ((pllmr & PLLMR_FWD_DIV_MASK) >> 29);
/*
* Determine FBK_DIV.
*/
sysInfo->pllFbkDiv = ((pllmr & PLLMR_FB_DIV_MASK) >> 25);
if (sysInfo->pllFbkDiv == 0) {
sysInfo->pllFbkDiv = 16;
}
/*
* Determine PLB_DIV.
*/
sysInfo->pllPlbDiv = ((pllmr & PLLMR_CPU_TO_PLB_MASK) >> 17) + 1;
/*
* Determine PCI_DIV.
*/
sysInfo->pllPciDiv = ((pllmr & PLLMR_PCI_TO_PLB_MASK) >> 13) + 1;
/*
* Determine EXTBUS_DIV.
*/
sysInfo->pllExtBusDiv = ((pllmr & PLLMR_EXB_TO_PLB_MASK) >> 11) + 2;
/*
* Determine OPB_DIV.
*/
sysInfo->pllOpbDiv = ((pllmr & PLLMR_OPB_TO_PLB_MASK) >> 15) + 1;
/*
* Check if PPC405GPr used (mask minor revision field)
*/
if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) {
/*
* Determine FWD_DIV B (only PPC405GPr with new mode strapping).
*/
sysInfo->pllFwdDivB = 8 - (pllmr & PLLMR_FWDB_DIV_MASK);
/*
* Determine factor m depending on PLL feedback clock source
*/
if (!(psr & PSR_PCI_ASYNC_EN)) {
if (psr & PSR_NEW_MODE_EN) {
/*
* sync pci clock used as feedback (new mode)
*/
m = 1 * sysInfo->pllFwdDivB * 2 * sysInfo->pllPciDiv;
} else {
/*
* sync pci clock used as feedback (legacy mode)
*/
m = 1 * sysInfo->pllFwdDivB * sysInfo->pllPlbDiv * sysInfo->pllPciDiv;
}
} else if (psr & PSR_NEW_MODE_EN) {
if (psr & PSR_PERCLK_SYNC_MODE_EN) {
/*
* PerClk used as feedback (new mode)
*/
m = 1 * sysInfo->pllFwdDivB * 2 * sysInfo->pllExtBusDiv;
} else {
/*
* CPU clock used as feedback (new mode)
*/
m = sysInfo->pllFbkDiv * sysInfo->pllFwdDiv;
}
} else if (sysInfo->pllExtBusDiv == sysInfo->pllFbkDiv) {
/*
* PerClk used as feedback (legacy mode)
*/
m = 1 * sysInfo->pllFwdDivB * sysInfo->pllPlbDiv * sysInfo->pllExtBusDiv;
} else {
/*
* PLB clock used as feedback (legacy mode)
*/
m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivB * sysInfo->pllPlbDiv;
}
sysInfo->freqVCOMhz = (1000000 * m) / sysClkPeriodPs;
sysInfo->freqProcessor = (sysInfo->freqVCOMhz * 1000000) / sysInfo->pllFwdDiv;
sysInfo->freqPLB = (sysInfo->freqVCOMhz * 1000000) /
(sysInfo->pllFwdDivB * sysInfo->pllPlbDiv);
} else {
/*
* Check pllFwdDiv to see if running in bypass mode where the CPU speed
* is equal to the 405GP SYS_CLK_FREQ. If not in bypass mode, check VCO
* to make sure it is within the proper range.
* spec: VCO = SYS_CLOCK x FBKDIV x PLBDIV x FWDDIV
* Note freqVCO is calculated in Mhz to avoid errors introduced by rounding.
*/
if (sysInfo->pllFwdDiv == 1) {
sysInfo->freqProcessor = CONFIG_SYS_CLK_FREQ * 1000000;
sysInfo->freqPLB = sysInfo->freqProcessor / sysInfo->pllPlbDiv;
} else {
sysInfo->freqVCOMhz = ( 1000000 *
sysInfo->pllFwdDiv *
sysInfo->pllFbkDiv *
sysInfo->pllPlbDiv
) / sysClkPeriodPs;
if (sysInfo->freqVCOMhz >= VCO_MIN
&& sysInfo->freqVCOMhz <= VCO_MAX) {
sysInfo->freqPLB = (ONE_BILLION /
((sysClkPeriodPs * 10) /
sysInfo->pllFbkDiv)) * 10000;
sysInfo->freqProcessor = sysInfo->freqPLB * sysInfo->pllPlbDiv;
}
}
}
}
unsigned long get_timer_freq(void)
{
struct ppc4xx_sys_info sys_info;
get_sys_info(&sys_info);
return sys_info.freqProcessor;
}
unsigned long get_pci_bus_freq(void)
{
struct ppc4xx_sys_info sys_info;
get_sys_info(&sys_info);
return sys_info.freqPLB;
}

59
src/cpu/ppc/ppc4xx/mem.c
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@ -1,59 +0,0 @@
#include <ppc.h>
#include <mem.h>
#include <console/console.h>
#define SDRAM0_CFGADDR 0x010
#define SDRAM0_CFGDATA 0x011
#define SDRAM0_B0CR 0x40
#define SDRAM0_B1CR 0x44
#define SDRAM0_B2CR 0x48
#define SDRAM0_B3CR 0x4C
#define BA_MASK 0xffc00000
#define BA_SHIFT 22
#define SZ_MASK 0x000e0000
#define SZ_SHIFT 17
#define AM_MASK 0x0000e000
#define AM_SHIFT 13
#define BE_MASK 0x00000001
#define BE_SHIFT 0
struct mem_range mem_bank[4];
void
getmemrange(int bank, unsigned int reg)
{
unsigned int val;
unsigned int size;
mtdcr(SDRAM0_CFGADDR, reg);
val = mfdcr(SDRAM0_CFGDATA);
if ((val & BE_MASK) == 0)
{
mem_bank[bank].basek = 0;
mem_bank[bank].sizek = 0;
return;
}
size = ((val & BA_MASK) >> BA_SHIFT);
mem_bank[bank].basek = size * 1024;
size = 4 << ((val & SZ_MASK) >> SZ_SHIFT);
mem_bank[bank].sizek = size * 1024;
printk_info("mem bank %d: basek %d, sizek %d\n", bank, mem_bank[bank].basek, mem_bank[bank].sizek);
}
struct mem_range *
sizeram(void)
{
getmemrange(0, SDRAM0_B0CR);
getmemrange(1, SDRAM0_B1CR);
getmemrange(2, SDRAM0_B2CR);
getmemrange(3, SDRAM0_B3CR);
return mem_bank;
}

33
src/cpu/ppc/ppc4xx/pci_bridge.c
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@ -1,33 +0,0 @@
/*
* Initialisation of the PCI bridge .
*/
#include <arch/io.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <console/console.h>
static void
pci_bridge_enable(struct device *dev)
{
printk_info("Configure PCI Bridge\n");
pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER);
pci_write_config16(dev, 0x60, 0x0f00);
printk_info("PCI Bridge configuration complete\n");
}
struct device_operations pci_bridge_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.enable = pci_bridge_enable,
.scan_bus = 0,
};
struct pci_driver pci_bridge_pci_driver __pci_driver = {
.ops = &pci_bridge_ops,
.device = PCI_DEVICE_ID_IBM_405GP,
.vendor = PCI_VENDOR_ID_IBM,
};

53
src/cpu/ppc/ppc4xx/pci_domain.c
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@ -1,53 +0,0 @@
/*
* Initialisation of the PCI bridge .
*/
#include <arch/io.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <console/console.h>
static void ram_resource(device_t dev, unsigned long index,
unsigned long basek, unsigned long sizek)
{
struct resource *resource;
if (!sizek) {
return;
}
resource = new_resource(dev, index);
resource->base = ((resource_t)basek) << 10;
resource->size = ((resource_t)sizek) << 10;
resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
static void pci_domain_set_resources(device_t dev)
{
int idx = 3; /* who knows? */
ram_resource(dev, idx, 0, CONFIG_EMBEDDED_RAM_SIZE>>10);
assign_resources(&dev->link[0]);
}
struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources,
.enable_resources = enable_childrens_resources,
.init = 0,
.scan_bus = pci_domain_scan_bus,
.ops_pci_bus = &pci_ppc_conf1
};
static void enable_dev(struct device *dev)
{
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
dev->ops = &pci_domain_ops;
}
}
struct chip_operations cpu_ppc_ppc4xx_ops = {
CHIP_NAME("PPC 4XX CPU")
.enable_dev = enable_dev,
};

111
src/cpu/ppc/ppc4xx/ppc4xx.inc
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@ -1,111 +0,0 @@
/*
* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
* Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*
* This source code has been made available to you by IBM on an AS-IS
* basis. Anyone receiving this source is licensed under IBM
* copyrights to use it in any way he or she deems fit, including
* copying it, modifying it, compiling it, and redistributing it either
* with or without modifications. No license under IBM patents or
* patent applications is to be implied by the copyright license.
*
* Any user of this software should understand that IBM cannot provide
* technical support for this software and will not be responsible for
* any consequences resulting from the use of this software.
*
* Any person who transfers this source code or any derivative work
* must include the IBM copyright notice, this paragraph, and the
* preceding two paragraphs in the transferred software.
*
* COPYRIGHT I B M CORPORATION 1995
* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
*
*/
/*
* Startup Code for IBM 4xx PowerPC based Embedded Boards
*
* Base on the U-Boot Startup Code
*
* The processor starts at 0xfffffffc and the code is executed
* from flash/rom.
*
* The purpose of this code is:
* - initalize the processor to a known state
* - turn on the I cache so things execute at a reasonable speed
* - set up a temporary stack in D cache
*/
#include "ppc4xx.h"
li r4,0x0000
mtspr sgr,r4
mtspr dcwr,r4
mtesr r4 /* clear Exception Syndrome Reg */
mttcr r4 /* clear Timer Control Reg */
mtxer r4 /* clear Fixed-Point Exception Reg */
mtevpr r4 /* clear Exception Vector Prefix Reg */
li r4,0x1000 /* set ME bit (Machine Exceptions) */
oris r4,r4,0x0002 /* set CE bit (Critical Exceptions) */
mtmsr r4 /* change MSR */
li r4,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in */
/* the dbsr is cleared by setting */
/* bits to 1) */
mtdbsr r4 /* clear/reset the dbsr */
/*
* Invalidate I and D caches. Enable I cache for defined memory
* regions to speed things up. Enable D cache for use as
* temporary memory until real memory is enabled.
*/
bl invalidate_icache
bl invalidate_dcache
/*
* Enable two 128MB cachable instruction regions
*
* 0x00000000 - 0x07FFFFFF
* 0xF8000000 - 0xFFFFFFFF
*/
lis r4,0x8000
ori r4,r4,0x0001
mticcr r4 /* instruction cache enable */
isync
/*
* Enable dcache region containing CONFIG_DCACHE_RAM_BASE
* On reset all regions are set to write-back, so we
* just leave them alone.
*
* dccr = (1 << (0x1F - (CONFIG_DCACHE_RAM_BASE >> 27))
*/
lis r4, CONFIG_DCACHE_RAM_BASE@ha
ori r4, r4, CONFIG_DCACHE_RAM_BASE@l
srwi r4, r4, 27
subfic r4, r4, 31
li r0, 1
slw r4, r0, r4
mtdccr r4 /* data cache enable */
sync

133
src/cpu/ppc/ppc4xx/sdram.c
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/*
* (C) Copyright 2002
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#include <ppc_asm.tmpl>
#include <ppc.h>
#include <ppc4xx.h>
#include <timer.h>
#include <clock.h>
#include <stdint.h>
#define CONFIGURE_SDRAM_BANK0
#ifdef CONFIGURE_SDRAM_BANK0
/*
* According to the PPC405GPr Users Manual, only non-reserved
* bits of SDRAM registers can be set. This means reading the
* contents and masking off bits to be set.
*/
#define CMD_BITS 0x80C00000
#define CMD_MASK 0xFFE00000
#define TR_BITS 0x010E8016
#define TR_MASK 0x018FC01F
#define B0CR_BITS 0x00084001
#define B0CR_MASK 0xFFCEE001
#define RTR_BITS 0x08080000
#define RTR_MASK 0xFFFF0000
#define ECCCF_BITS 0x00000000
#define ECCCF_MASK 0x00F00000
#define PMIT_BITS 0x0F000000
#define PMIT_MASK 0xFFC00000
#define mfsdram0(reg, data) mtdcr(memcfga,reg);data = mfdcr(memcfgd)
#define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data)
#define set_sdram0(reg, val) \
mfsdram0(reg, reg32); \
reg32 &= ~(val##_MASK); \
reg32 |= (val##_BITS); \
mtsdram0(reg, reg32)
/*-----------------------------------------------------------------------
*/
void memory_init(void)
{
#if 0
unsigned long speed;
unsigned long sdtr1;
#endif
uint32_t reg32;
#if 0
/*
* Determine SDRAM speed
*/
speed = get_pci_bus_freq(); /* parameter not used on ppc4xx */
/*
* Support for 100MHz and 133MHz SDRAM
*/
if (speed > 100000000) {
/*
* 133 MHz SDRAM
*/
sdtr1 = 0x01074015;
rtr = 0x07f00000;
} else {
/*
* default: 100 MHz SDRAM
*/
sdtr1 = 0x0086400d;
rtr = 0x05f00000;
}
#endif
/*
* Disable memory controller.
*/
/* TODO: work out why this trashes cache ram */
//mtsdram0(mem_mcopt1, 0x00000000);
#if CONFIG_EMBEDDED_RAM_SIZE==128*1024*1024
/* TODO */
#elif CONFIG_EMBEDDED_RAM_SIZE==64*1024*1024
set_sdram0(mem_sdtr1, TR);
set_sdram0(mem_mb0cf, B0CR);
set_sdram0(mem_rtr, RTR);
set_sdram0(mem_ecccf, ECCCF);
set_sdram0(mem_pmit, PMIT);
#elif CONFIG_EMBEDDED_RAM_SIZE==32*1024*1024
/* TODO */
#elif CONFIG_EMBEDDED_RAM_SIZE==16*1024*1024
/* TODO */
#endif
/*
* Wait for 200us
*/
udelay(200);
/*
* Set memory controller options reg, MCOPT1.
* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
* read/prefetch.
*/
set_sdram0(mem_mcopt1, CMD);
/*
* Wait for 10ms
*/
udelay(10000);
}
#endif /* CONFIGURE_SDRAM_BANK0 */

27
src/cpu/ppc/ppc7xx/Config.lb
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@ -1,27 +0,0 @@
##
## CPU initialization
##
uses CONFIG_RAMBASE
uses CONFIG_USE_DCACHE_RAM
uses CONFIG_DCACHE_RAM_BASE
uses CONFIG_DCACHE_RAM_SIZE
##
## PPC7XX always uses cache ram for initial setup
##
default CONFIG_USE_DCACHE_RAM=1
## Set dcache ram above coreboot image
default CONFIG_DCACHE_RAM_BASE=CONFIG_RAMBASE+0x100000
## Dcache size is 16Kb
default CONFIG_DCACHE_RAM_SIZE=16384
initinclude "FAMILY_INIT" cpu/ppc/ppc7xx/ppc7xx.inc
# Only TotalImpact Briq uses the ppc7xx and it brings its own clock.o
# so we comment this out for now:
# object clock.o
object cache.S
#initobject clock.o
initobject cache.S
dir /cpu/simple_init

23
src/cpu/ppc/ppc7xx/cache.S
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@ -1,23 +0,0 @@
#define ASM
#include "ppcreg.h"
#include <ppc_asm.tmpl>
#define NUM_CACHE_LINES 128*8
#define L1_CACHE_LINE_SIZE 32
#define cache_flush_buffer 0x1000
/*
* Flush data cache
* Do this by just reading lots of stuff into the cache.
*/
.globl flush_dcache
flush_dcache:
lis r3,cache_flush_buffer@h
ori r3,r3,cache_flush_buffer@l
li r4,NUM_CACHE_LINES
mtctr r4
0: lwz r4,0(r3)
addi r3,r3,L1_CACHE_LINE_SIZE
bdnz 0b
blr

27
src/cpu/ppc/ppc7xx/clock.c
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@ -1,27 +0,0 @@
#include <ppc.h>
static int PLL_multiplier[] = {
25, /* 0000 - 2.5x */
75, /* 0001 - 7.5x */
70, /* 0010 - 7x */
10, /* 0011 - bypass */
20, /* 0100 - 2x */
65, /* 0101 - 6.5x */
100, /* 0110 - 10x */
45, /* 0111 - 4.5x */
30, /* 1000 - 3x */
55, /* 1001 - 5.5x */
40, /* 1010 - 4x */
50, /* 1011 - 5x */
80, /* 1100 - 8x */
60, /* 1101 - 6x */
35, /* 1110 - 3.5x */
0, /* 1111 - off */
};
unsigned long
get_timer_freq(void)
{
unsigned long clock = CONFIG_SYS_CLK_FREQ * 1000000;
return clock * PLL_multiplier[ppc_gethid1() >> 28] / 10;
}

170
src/cpu/ppc/ppc7xx/ppc7xx.inc
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@ -1,170 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2000 AG Electronics Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/*
* The aim of this code is to bring the machine from power-on to the point
* where we can jump to the the main coreboot entry point hardwaremain()
* which is written in C.
*
* At power-on, we have no RAM, a memory-mapped I/O space, and we are executing
* out of ROM, generally at 0xfff00100.
*
* Before we jump to harwaremain() we want to do the following:
*
* - enable L1 I/D caches, otherwise performance will be slow
* - set up DBATs for the following regions:
* - RAM (generally 0x00000000 -> 0x7fffffff)
* - ROM (CONFIG_ROMBASE -> CONFIG_ROMBASE + CONFIG_ROM_SIZE)
* - I/O (generally 0xfc000000 -> 0xfdffffff)
* - the main purpose for setting up the DBATs is so the I/O region
* can be marked cache inhibited/write through
* - set up IBATs for RAM and ROM
*
*/
#include <ppc750.h>
#define BSP_IOREGION1 0x80000000
#define BSP_IOMASK1 BAT_BL_256M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
#define BSP_IOREGION2 0xFD000000
#define BSP_IOMASK2 BAT_BL_64M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
isync
/*
* Disable dcache and MMU, so we're in a known state
*/
li r0, 0
sync
mtspr HID0, r0
sync
mtmsr r0
isync
/*
* Invalidate D & I BATS
*/
mtibatu 0, r0
mtibatu 1, r0
mtibatu 2, r0
mtibatu 3, r0
isync
mtdbatu 0, r0
mtdbatu 1, r0
mtdbatu 2, r0
mtdbatu 3, r0
isync
/*
* Clear segment registers (coreboot doesn't use these)
*/
li r3, 15
1: mtsrin r3, r0
subic. r3, r3, 1
bge 1b
isync
/*
* Set up DBATs
*
* DBAT0 covers RAM (0 -> 0x0FFFFFFF) (256Mb)
* DBAT1 covers PCI memory and ROM (0xFD000000 -> 0xFFFFFFFF) (64Mb)
* DBAT2 covers PCI memory (0x80000000 -> 0x8FFFFFFF) (256Mb)
* DBAT3 is not used
*/
lis r2, 0@h
ori r3, r2, BAT_BL_256M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
ori r2, r2, BAT_READ_WRITE | BAT_GUARDED
mtdbatu 0, r3
mtdbatl 0, r2
isync
lis r2, BSP_IOREGION2@h
ori r3, r2, BAT_BL_64M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
ori r2, r2, BAT_CACHE_INHIBITED | BAT_GUARDED | BAT_READ_WRITE
mtdbatu 1, r3
mtdbatl 1, r2
isync
lis r2, BSP_IOREGION1@h
ori r3, r2, BAT_BL_256M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
ori r2, r2, BAT_CACHE_INHIBITED | BAT_GUARDED | BAT_READ_WRITE
mtdbatu 2, r3
mtdbatl 2, r2
isync
/*
* IBATS
*
* IBAT0 covers RAM (0 -> 256Mb)
* IBAT1 covers ROM (CONFIG_ROMBASE -> CONFIG_ROMBASE+CONFIG_ROM_SIZE)
*/
lis r2, 0@h
ori r3, r2, BAT_BL_256M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
ori r2, r2, BAT_READ_WRITE
mtibatu 0, r3
mtibatl 0, r2
isync
lis r2, CONFIG_ROMBASE@h
#if CONFIG_ROM_SIZE > 1048576
ori r3, r2, BAT_BL_16M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
#else
ori r3, r2, BAT_BL_1M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
#endif
ori r2, r2, BAT_READ_ONLY
mtibatu 1, r3
mtibatl 1, r2
isync
/*
* Enable MMU
*/
mfmsr r2
ori r2, r2, MSR_DR | MSR_IR
mtmsr r2
isync
sync
/*
* Enable and invalidate the L1 icache
*/
mfspr r2, HID0
ori r2, r2, HID0_ICE | HID0_ICFI
isync
mtspr HID0, r2
/*
* Enable and invalidate the L1 dcache
*/
mfspr r2, HID0
ori r2, r2, HID0_DCE | HID0_DCFI
sync
mtspr HID0, r2
/*
* Initialize data cache blocks
* (assumes cache block size of 32 bytes)
*/
lis r1, CONFIG_DCACHE_RAM_BASE@h
ori r1, r1, CONFIG_DCACHE_RAM_BASE@l
li r3, (CONFIG_DCACHE_RAM_SIZE / 32)
mtctr r3
0: dcbz r0, r1
addi r1, r1, 32
bdnz 0b

15
src/cpu/ppc/ppc970/Config.lb
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@ -1,15 +0,0 @@
##
## CPU initialization
##
uses CONFIG_RAMBASE
uses CONFIG_USE_DCACHE_RAM
##
## Assumes RAM already initialiazed
## This is true for the Apache board, but may
## not be for other 970 systems.
##
default CONFIG_USE_DCACHE_RAM=0
initinclude "FAMILY_INIT" cpu/ppc/ppc970/ppc970.inc

365
src/cpu/ppc/ppc970/ppc970.inc
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@ -1,365 +0,0 @@
/*bsp_970fx/bootlib/init_core.s, pibs_970, pibs_970_1.0 1/14/05 14:58:41*/
/*----------------------------------------------------------------------------+
| COPYRIGHT I B M CORPORATION 2002, 2004
| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
| US Government Users Restricted Rights - Use, duplication or
| disclosure restricted by GSA ADP Schedule Contract with
| IBM Corp.
+----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------+
| PPC970FX BSP for EPOS
| Author: Maciej P. Tyrlik
| Component: Boot library.
| File: init_core.s
| Purpose: Basic PPC405 core initialization.
| Changes:
| Date: Comment:
| ----- --------
| 29-Jan-02 Created MPT
| 30-Jan-02 Completed MPT
| 19-Apr-02 Changed some instructions to macros so that new GCC AS worksMPT
| 23-Apr-02 Removed critical interrupt enabling after rfi MPT
| 31-Jul-02 Fixed data cache invalidate code MPT
| 01-Feb-03 Ported to Argan 7XXFX CRB
| 07-Aug-03 Ported to PPC7XXGX CRB
| 12-Sep-03 Removed PVR definitions, now in board include file MCG
| 16-Sep-03 Do not enable HID0[MUM] or L2CR[L2CE] if 7XXGX DD1.0 MCG
| 31-Oct-03 Enable cache for MV64460 integrated SRAM MCG
| 07-Jan-04 Initialize FPRs to avoid errata. MCG
| 10-Feb-04 Port to PPC970FX MPT
+----------------------------------------------------------------------------*/
#include <ppc970.h>
/*----------------------------------------------------------------------------+
| Local defines.
+----------------------------------------------------------------------------*/
#define INITIAL_SLB_VSID_VAL 0x0000000000000C00
#define INITIAL_SLB_ESID_VAL 0x0000000008000000
#define INITIAL_SLB_INVA_VAL 0x0000000000000000
/*----------------------------------------------------------------------------+
| Init_core. Assumption: hypervisor on, 64-bit on, HID1[10]=0, HID4[23]=0.
| Data cahability must be turned on. Instruction cahability must be off.
+----------------------------------------------------------------------------*/
/*--------------------------------------------------------------------+
| Set time base to 0.
+--------------------------------------------------------------------*/
addi r4,r0,0x0000
mtspr SPR_TBU_WRITE,r4
mtspr SPR_TBL_WRITE,r4
/*--------------------------------------------------------------------+
| Set HID1[10] to 0 (instruction cache off) and set HID4[23] to 0 (data
| cache on), set HID4[DC_SET1] and HID4[DC_SET2] to 0.
+--------------------------------------------------------------------*/
LOAD_64BIT_VAL(r4,HID1_EN_IC)
nor r4,r4,r4
mfspr r5,SPR_HID1
isync
and r5,r5,r4
mtspr SPR_HID1,r5
mtspr SPR_HID1,r5
isync
LOAD_64BIT_VAL(r4,HID4_RM_CI|HID4_DC_SET1|HID4_DC_SET2)
nor r4,r4,r4
mfspr r5,SPR_HID4
LOAD_64BIT_VAL(r6,HID4_L1DC_FLSH)
isync
and r5,r5,r4
or r5,r5,r6
sync
mtspr SPR_HID4,r5
isync
/*--------------------------------------------------------------------+
| Clear the flash invalidate L1 data cache bit in HID4.
+--------------------------------------------------------------------*/
nor r6,r6,r6
and r5,r5,r6
sync
mtspr SPR_HID4,r5
isync
/*--------------------------------------------------------------------+
| Clear and set up some registers.
+--------------------------------------------------------------------*/
addi r4,r0,0x0000
mtxer r4
/*--------------------------------------------------------------------+
| Invalidate SLB. First load SLB with known values then perform
| invalidate. Invalidate will clear the D-ERAT and I-ERAT. The SLB
| is 64 entry fully associative. On power on D-ERAT and I-ERAT are all
| set to invalid values.
+--------------------------------------------------------------------*/
addi r5,r0,SLB_SIZE
mtctr r5
LOAD_64BIT_VAL(r6,INITIAL_SLB_VSID_VAL)
LOAD_64BIT_VAL(r7,INITIAL_SLB_ESID_VAL)
addis r8,r0,0x1000
0: slbmte r6,r7
addi r6,r6,0x1000
add r7,r7,r8
addi r7,r7,0x0001
bdnz 0b
mtctr r5
LOAD_64BIT_VAL(r6,INITIAL_SLB_INVA_VAL)
1: slbie r6
add r6,r6,r8
bdnz 1b
/*--------------------------------------------------------------------+
| Load SLB. Following is the initial memory map.
| Entry(6) ESID(36) VSID
| 0x0 0x000000000 0x0000000000000 (large page cachable)
| 0x1 0x00000000F 0x000000000000F (small non-cachable, G)
| at 0x00000000 there will be 48MB mapped (SDRAM)
| at 0xF8000000 there will be 16MB mapped (NB)
| at 0xF4000000 there will be 64KB mapped (I/O space)
| at 0xFF000000 there will be 16MB or 1MB mapped (FLASH)
+--------------------------------------------------------------------*/
addi r6,r0,0x0100
addis r7,r0,0x0800
slbmte r6,r7
addi r6,r0,0x0000
ori r6,r6,0xF000
addi r7,r0,0x0001
oris r7,r7,0xF800
slbmte r6,r7
/*--------------------------------------------------------------------+
| Invalidate all 1024 instruction and data TLBs (4 way)
+--------------------------------------------------------------------*/
addi r8,r0,0x0100
mtspr CTR,r8
addi r8,r0,0x0000
2: TLBIEL(r8)
addi r8,r8,0x1000
bdnz 2b
ptesync
/*--------------------------------------------------------------------+
| Dcbz the page table space. Calculate SDR1 address. Store SDR1
| address in r30.
+--------------------------------------------------------------------*/
mfspr r3,SPR_PIR
cmpi cr0,1,r3,0x0000
bne 3f
addis r3,r0,INITIAL_PAGE_TABLE_ADDR_CPU0@h
ori r3,r3,INITIAL_PAGE_TABLE_ADDR_CPU0@l
b 4f
3: addis r3,r0,INITIAL_PAGE_TABLE_ADDR_CPU1@h
ori r3,r3,INITIAL_PAGE_TABLE_ADDR_CPU1@l
4: addis r4,r0,INITIAL_PAGE_TABLE_SIZE@h
ori r4,r4,INITIAL_PAGE_TABLE_SIZE@l
rlwinm r5,r4,14,14,31
cntlzw r5,r5
subfic r5,r5,31
or r30,r3,r5
bl .ppcDcbz_area
/*--------------------------------------------------------------------+
| Setup 0x00000000FFFFFFFF mask in r29.
+--------------------------------------------------------------------*/
addi r29,r0,0x0001
rldicl r29,r29,32,31
addi r29,r29,-1
/*--------------------------------------------------------------------+
| Setup 48MB of addresses in DRAM in page table (3 large PTE). The
| parameters to p_ptegg are: r3 = lp, r4 = ea, r5 = sdr1, r6 = vsid.
+--------------------------------------------------------------------*/
addi r3,r0,0x0001
addi r4,r0,0x0000
ori r5,r30,0x0000
addi r6,r0,0x0000
bl .p_ptegg
addi r4,r0,0x0001
stw r4,0x0004(r3)
addi r4,r0,0x0180
stw r4,0x000C(r3)
/*--------------------------------------------------------------------+
| Second 16MB is mapped here.
+--------------------------------------------------------------------*/
addi r3,r0,0x0001
addis r4,r0,0x0100
ori r5,r30,0x0000
addi r6,r0,0x0000
bl .p_ptegg
addi r4,r0,0x0101
stw r4,0x0004(r3)
addis r4,r0,0x0100
ori r4,r4,0x0180
stw r4,0x000C(r3)
/*--------------------------------------------------------------------+
| Third 16MB is mapped here.
+--------------------------------------------------------------------*/
addi r3,r0,0x0001
addis r4,r0,0x0200
ori r5,r30,0x0000
addi r6,r0,0x0000
bl .p_ptegg
addi r4,r0,0x0201
stw r4,0x0004(r3)
addis r4,r0,0x0200
ori r4,r4,0x0180
stw r4,0x000C(r3)
/*--------------------------------------------------------------------+
| Setup 64KB of addresses in I/O space (0xF4000000).
+--------------------------------------------------------------------*/
addi r3,r0,0x0010
mtctr r3
addis r31,r0,0xF400
and r31,r31,r29
5: addi r3,r0,0x0000
ori r4,r31,0x0000
ori r5,r30,0x0000
addi r6,r0,0x000F
bl .p_ptegg
addi r6,r3,0x0080
6: lwz r4,0x0004(r3)
cmpli cr0,1,r4,0x0000
beq 8f
addi r3,r3,0x0010
cmp cr0,1,r3,r6
blt 6b
7: b 7b
8: rlwinm r4,r31,16,4,24
ori r4,r4,0x0001
stw r4,0x0004(r3)
ori r4,r31,0x01AC
stw r4,0x000C(r3)
addi r31,r31,0x1000
bdnz 5b
/*--------------------------------------------------------------------+
| Setup 16MB of addresses in NB register space (0xF8000000).
+--------------------------------------------------------------------*/
addi r3,r0,0x1000
mtctr r3
addis r31,r0,0xF800
and r31,r31,r29
9: addi r3,r0,0x0000
ori r4,r31,0x0000
ori r5,r30,0x0000
addi r6,r0,0x000F
bl .p_ptegg
addi r6,r3,0x0080
10: lwz r4,0x0004(r3)
cmpli cr0,1,r4,0x0000
beq 12f
addi r3,r3,0x0010
cmp cr0,1,r3,r6
blt 10b
11: b 11b
12: rlwinm r4,r31,16,4,24
ori r4,r4,0x0001
stw r4,0x0004(r3)
ori r4,r31,0x01AC
stw r4,0x000C(r3)
addi r31,r31,0x1000
bdnz 9b
/*--------------------------------------------------------------------+
| Setup 16MB or 1MB of addresses in ROM (at 0xFF000000 or 0xFFF00000).
+--------------------------------------------------------------------*/
mfspr r3,SPR_HIOR
LOAD_64BIT_VAL(r4,BOOT_BASE_AS)
cmpd cr0,r3,r4
beq 13f
addi r3,r0,0x0100
mtctr r3
addis r31,r0,0xFFF0
b 14f
13: addi r3,r0,0x1000
mtctr r3
addis r31,r0,0xFF00
14: and r31,r31,r29
15: addi r3,r0,0x0000
ori r4,r31,0x0000
ori r5,r30,0x0000
addi r6,r0,0x000F
bl .p_ptegg
addi r6,r3,0x0080
16: lwz r4,0x0004(r3)
cmpli cr0,1,r4,0x0000
beq 18f
addi r3,r3,0x0010
cmp cr0,1,r3,r6
blt 16b
17: b 17b
18: rlwinm r4,r31,16,4,24
ori r4,r4,0x0001
stw r4,0x0004(r3)
ori r4,r31,0x01A3
stw r4,0x000C(r3)
addi r31,r31,0x1000
bdnz 15b
/*--------------------------------------------------------------------+
| Synchronize after setting up page table.
+--------------------------------------------------------------------*/
ptesync
/*--------------------------------------------------------------------+
| Set the SDR1 register.
+--------------------------------------------------------------------*/
mtspr SPR_SDR1,r30
/*--------------------------------------------------------------------+
| Clear SRR0, SRR1.
+--------------------------------------------------------------------*/
addi r0,r0,0x0000
mtspr SPR_SRR0,r0
mtspr SPR_SRR1,r0
/*--------------------------------------------------------------------+
| Setup for subsequent MSR[ME] initialization to enable machine checks
| and translation.
+--------------------------------------------------------------------*/
mfmsr r3
ori r3,r3,(MSR_ME|MSR_IS|MSR_DS|MSR_FP)
mtsrr1 r3
mtmsrd r3,0
isync
/*--------------------------------------------------------------------+
| Setup HID registers (HID0, HID1, HID4, HID5). When HIOR is set to
| 0 HID0 external time base bit is inherited from current HID0. When
| HIOR is set to FLASH_BASE_INTEL_AS then HID0 external time base bit
| is set to 1 in order to indicate that the tiembase is driven by
| external source. When HIOR is greater than FLASH_BASE_INTEL_AS then
| HID0 external time base bit is set to 0 in order to indicate that the
| tiembase is driven from internal clock.
+--------------------------------------------------------------------*/
LOAD_64BIT_VAL(r6,HID0_EXT_TB_EN)
LOAD_64BIT_VAL(r7,FLASH_BASE_INTEL_AS)
mfspr r5,SPR_HIOR
cmpdi cr0,r5,0x0000
beq 19f
cmpd cr0,r5,r7
beq 20f
addi r8,r0,0x0000
b 21f
20: ori r8,r6,0x0000
b 21f
19: mfspr r5,SPR_HID0
and r8,r5,r6
21: LOAD_64BIT_VAL(r4,HID0_PREFEAR)
andc r4,r4,r6
or r4,r4,r8
sync
mtspr SPR_HID0,r4
mfspr r4,SPR_HID0
mfspr r4,SPR_HID0
mfspr r4,SPR_HID0
mfspr r4,SPR_HID0
mfspr r4,SPR_HID0
mfspr r4,SPR_HID0
LOAD_64BIT_VAL(r4,HID1_PREFEAR)
mtspr SPR_HID1,r4
mtspr SPR_HID1,r4
isync
LOAD_64BIT_VAL(r4,HID4_PREFEAR)
sync
mtspr SPR_HID4,r4
isync
sync
LOAD_64BIT_VAL(r4,HID5_PREFEAR)
mtspr SPR_HID5,r4
isync
/*--------------------------------------------------------------------+
| Synchronize memory accesses (sync).
+--------------------------------------------------------------------*/
sync
LOAD_64BIT_VAL(r0,.init_chip)
mfspr r1,SPR_HIOR
or r0,r0,r1
eieio
mtspr SPR_SRR0,r0
rfid

1
src/cpu/simple_init/Config.lb
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@ -1 +0,0 @@
object simple_cpu_init.o

1
src/cpu/simple_init/Makefile.inc
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obj-y += simple_cpu_init.o

27
src/cpu/simple_init/simple_cpu_init.c
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@ -1,27 +0,0 @@
#include <console/console.h>
#include <device/device.h>
#include <device/path.h>
#include <cpu/cpu.h>
#if CONFIG_SMP
#error "This Configuration does not support SMP"
#endif
void initialize_cpus(struct bus *cpu_bus)
{
struct device_path cpu_path;
struct cpu_info *info;
/* Find the info struct for this cpu */
info = cpu_info();
/* Get the device path of the boot cpu */
cpu_path.type = DEVICE_PATH_CPU;
cpu_path.cpu.id = 0;
/* Find the device struct for the boot cpu */
info->cpu = alloc_find_dev(cpu_bus, &cpu_path);
/* Initialize the bootstrap processor */
cpu_initialize();
}