soc/amd/picasso/acpi: move remaining parts of sb_pic0_fch.asl to soc.asl

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I785abfc90c99b58c11d57847573f550fcea1f774
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>

src/soc/amd/picasso/acpi/sb_pci0_fch.asl

@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* System Bus */
-/*  _SB.PCI0 */
-
-/* 0:14.3 - LPC */
-#include <soc/amd/common/acpi/lpc.asl>
-#include <soc/amd/common/acpi/platform.asl>

src/soc/amd/picasso/acpi/soc.asl

@@ -9,7 +9,8 @@ Scope(PCI0) {
 	#include "northbridge.asl"
 
 	/* Describe the AMD Fusion Controller Hub */
-	#include "sb_pci0_fch.asl"
+	#include <soc/amd/common/acpi/lpc.asl>
+	#include <soc/amd/common/acpi/platform.asl>
 }
 
 /* PCI IRQ mapping for the Southbridge */